GPIO Simulation Results

Sunday May 05 2024 19:05:13 UTC

GitHub Revision: d0c52cdadd

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 81579111587980121648949789282063322266496016209500883225240730864920651071561

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.540s	418.733us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.400s	1.257ms	50	50	100.00
		gpio_smoke_en_cdc_prim	1.780s	96.942us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.600s	46.710us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.660s	17.965us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.660s	26.869us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	2.960s	81.854us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.870s	146.178us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.490s	34.165us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.660s	26.869us	20	20	100.00
		gpio_csr_aliasing	0.870s	146.178us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.280s	155.046us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.430s	261.339us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	1.000s	85.701us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.470s	87.274us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.440s	232.517us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.690s	96.667us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	27.280s	4.207ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.420s	1.494ms	50	50	100.00
V2	full_random	gpio_full_random	1.140s	595.922us	50	50	100.00
V2	stress_all	gpio_stress_all	4.041m	17.272ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.640s	11.218us	50	50	100.00
V2	intr_test	gpio_intr_test	0.720s	45.736us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.110s	229.541us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.110s	229.541us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.660s	26.869us	20	20	100.00
		gpio_same_csr_outstanding	0.860s	42.539us	20	20	100.00
		gpio_csr_aliasing	0.870s	146.178us	5	5	100.00
		gpio_csr_hw_reset	0.660s	17.965us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.660s	26.869us	20	20	100.00
		gpio_same_csr_outstanding	0.860s	42.539us	20	20	100.00
		gpio_csr_aliasing	0.870s	146.178us	5	5	100.00
		gpio_csr_hw_reset	0.660s	17.965us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.510s	404.016us	20	20	100.00
		gpio_sec_cm	0.980s	1.009ms	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.510s	404.016us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	45.479m	161.351ms	22	50	44.00
V3		TOTAL			22	50	44.00
		TOTAL			942	970	97.11

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 28 failures:
  • Test gpio_stress_all_with_rand_reset has 28 failures.

    • 1.gpio_stress_all_with_rand_reset.46715386422064764176793185096936696102545097875195615071544534418721347089141
      Line 969, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6711293548 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 6711293548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.gpio_stress_all_with_rand_reset.74229580515783225399897287655128942176891204771121843314108897701505294976052
      Line 14604, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/2.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 37486091074 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10003 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 37486091074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 26 more failures.

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