GPIO Simulation Results

Thursday May 09 2024 19:02:32 UTC

GitHub Revision: 9656691e03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 30170103562476460183108208532025718695603957360441815475011549460912256789439

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.450s	332.514us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.440s	93.472us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.430s	204.618us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.390s	159.646us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.700s	66.829us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.690s	13.478us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.470s	691.903us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.920s	144.361us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.650s	32.583us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.690s	13.478us	20	20	100.00
		gpio_csr_aliasing	0.920s	144.361us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.400s	76.013us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.240s	362.477us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	0.910s	125.348us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.460s	109.242us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.420s	161.991us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.590s	99.922us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	28.020s	3.429ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	5.930s	2.067ms	50	50	100.00
V2	full_random	gpio_full_random	1.090s	78.237us	50	50	100.00
V2	stress_all	gpio_stress_all	4.017m	16.490ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.630s	46.513us	50	50	100.00
V2	intr_test	gpio_intr_test	0.690s	19.941us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.060s	60.410us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.060s	60.410us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.690s	13.478us	20	20	100.00
		gpio_same_csr_outstanding	0.900s	66.125us	20	20	100.00
		gpio_csr_aliasing	0.920s	144.361us	5	5	100.00
		gpio_csr_hw_reset	0.700s	66.829us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.690s	13.478us	20	20	100.00
		gpio_same_csr_outstanding	0.900s	66.125us	20	20	100.00
		gpio_csr_aliasing	0.920s	144.361us	5	5	100.00
		gpio_csr_hw_reset	0.700s	66.829us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.430s	239.473us	20	20	100.00
		gpio_sec_cm	1.030s	238.587us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.430s	239.473us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	47.977m	322.292ms	18	50	36.00
V3		TOTAL			18	50	36.00
		TOTAL			938	970	96.70

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 32 failures:
  • Test gpio_stress_all_with_rand_reset has 32 failures.

    • 1.gpio_stress_all_with_rand_reset.47318928955848114016442489338829106077340215379274748099160333550525727135276
      Line 3216, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 13029116437 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 13029116437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.gpio_stress_all_with_rand_reset.34603572943803813352986077282402652804315685280770221244844462566532882183299
      Line 3491, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/4.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 51927938289 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 51927938289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 30 more failures.

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