GPIO Simulation Results

Sunday May 12 2024 19:02:35 UTC

GitHub Revision: 69c572b503

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 72674276607041733394622960695970595070180537542023880499199659375034056632550

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.630s	140.111us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.520s	389.948us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.470s	350.332us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.510s	155.532us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.690s	15.210us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.660s	53.333us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.170s	994.650us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.870s	50.761us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.650s	135.189us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.660s	53.333us	20	20	100.00
		gpio_csr_aliasing	0.870s	50.761us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.340s	147.951us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.280s	398.406us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	1.000s	96.969us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.510s	465.493us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.530s	307.258us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.920s	186.569us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	28.350s	19.893ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.300s	1.065ms	50	50	100.00
V2	full_random	gpio_full_random	1.090s	95.200us	50	50	100.00
V2	stress_all	gpio_stress_all	3.689m	20.639ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.630s	15.995us	50	50	100.00
V2	intr_test	gpio_intr_test	0.680s	12.375us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.030s	145.246us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.030s	145.246us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.660s	53.333us	20	20	100.00
		gpio_same_csr_outstanding	0.880s	22.377us	20	20	100.00
		gpio_csr_aliasing	0.870s	50.761us	5	5	100.00
		gpio_csr_hw_reset	0.690s	15.210us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.660s	53.333us	20	20	100.00
		gpio_same_csr_outstanding	0.880s	22.377us	20	20	100.00
		gpio_csr_aliasing	0.870s	50.761us	5	5	100.00
		gpio_csr_hw_reset	0.690s	15.210us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.590s	108.062us	20	20	100.00
		gpio_sec_cm	1.000s	118.157us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.590s	108.062us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	38.621m	196.810ms	23	50	46.00
V3		TOTAL			23	50	46.00
		TOTAL			943	970	97.22

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 27 failures:
  • Test gpio_stress_all_with_rand_reset has 27 failures.

    • 0.gpio_stress_all_with_rand_reset.38625770724553126069682874584453699581249481987858215533065523871865730206229
      Line 9087, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 38951104468 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 38951104468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.gpio_stress_all_with_rand_reset.55828029345866377754242277822172021997129257931773780067665634137333296984445
      Line 5346, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 420783427444 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 420783427444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 25 more failures.

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