GPIO Simulation Results

Tuesday May 14 2024 19:02:33 UTC

GitHub Revision: 00fe426038

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56275124637035941820967954627144971699378360917446801543187025394370981034792

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.500s	118.401us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.420s	53.644us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.580s	99.809us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.550s	163.499us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.710s	16.631us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.650s	22.527us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.470s	661.093us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.850s	60.404us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.190s	102.898us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.650s	22.527us	20	20	100.00
		gpio_csr_aliasing	0.850s	60.404us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.390s	120.382us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.440s	69.912us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	1.000s	30.677us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.470s	78.373us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.760s	949.747us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.710s	190.954us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	27.950s	3.837ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	7.410s	1.788ms	50	50	100.00
V2	full_random	gpio_full_random	1.180s	281.371us	50	50	100.00
V2	stress_all	gpio_stress_all	4.083m	78.617ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.700s	15.434us	50	50	100.00
V2	intr_test	gpio_intr_test	0.660s	19.205us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	2.990s	577.923us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	2.990s	577.923us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.650s	22.527us	20	20	100.00
		gpio_same_csr_outstanding	0.960s	70.136us	20	20	100.00
		gpio_csr_aliasing	0.850s	60.404us	5	5	100.00
		gpio_csr_hw_reset	0.710s	16.631us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.650s	22.527us	20	20	100.00
		gpio_same_csr_outstanding	0.960s	70.136us	20	20	100.00
		gpio_csr_aliasing	0.850s	60.404us	5	5	100.00
		gpio_csr_hw_reset	0.710s	16.631us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.540s	105.814us	20	20	100.00
		gpio_sec_cm	0.990s	101.019us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.540s	105.814us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	30.479m	134.812ms	14	50	28.00
V3		TOTAL			14	50	28.00
		TOTAL			934	970	96.29

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 36 failures:
  • Test gpio_stress_all_with_rand_reset has 36 failures.

    • 0.gpio_stress_all_with_rand_reset.66187984195150577989097116132601550013439194701314060667035658717046220974169
      Line 3421, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 65545427628 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 65545427628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.gpio_stress_all_with_rand_reset.84319920190303034064586410636778134834151717593163060449917870530434090826820
      Line 6476, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 92134341203 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 92134341203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 34 more failures.

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