GPIO Simulation Results

Thursday May 16 2024 19:02:11 UTC

GitHub Revision: 349bab6601

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 60729333463373082946889975499553948547086354767408862399987151421185145065082

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.670s	76.222us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.640s	149.761us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.600s	75.131us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.680s	216.167us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.690s	57.562us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.690s	27.134us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.670s	757.284us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.880s	35.581us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	2.090s	43.400us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.690s	27.134us	20	20	100.00
		gpio_csr_aliasing	0.880s	35.581us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.540s	61.931us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.490s	72.073us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	1.080s	176.531us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.660s	88.582us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.840s	336.511us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	4.330s	93.769us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	29.240s	926.124us	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.450s	472.185us	50	50	100.00
V2	full_random	gpio_full_random	1.130s	253.851us	50	50	100.00
V2	stress_all	gpio_stress_all	3.524m	94.380ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.640s	37.669us	50	50	100.00
V2	intr_test	gpio_intr_test	0.680s	25.700us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.260s	217.082us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.260s	217.082us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.690s	27.134us	20	20	100.00
		gpio_same_csr_outstanding	0.890s	344.011us	20	20	100.00
		gpio_csr_aliasing	0.880s	35.581us	5	5	100.00
		gpio_csr_hw_reset	0.690s	57.562us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.690s	27.134us	20	20	100.00
		gpio_same_csr_outstanding	0.890s	344.011us	20	20	100.00
		gpio_csr_aliasing	0.880s	35.581us	5	5	100.00
		gpio_csr_hw_reset	0.690s	57.562us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.530s	148.155us	20	20	100.00
		gpio_sec_cm	1.010s	381.284us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.530s	148.155us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	43.611m	121.148ms	19	50	38.00
V3		TOTAL			19	50	38.00
		TOTAL			939	970	96.80

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 31 failures:
  • Test gpio_stress_all_with_rand_reset has 31 failures.

    • 0.gpio_stress_all_with_rand_reset.114625917064928214519574757446649278455239051252811878407890967194131272032578
      Line 10555, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 54479023709 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 54479023709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.gpio_stress_all_with_rand_reset.26835297933813937834068392632415338221162286886312889074383950630440275344683
      Line 3773, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 29967079548 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 29967079548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 29 more failures.

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