GPIO Simulation Results

Sunday May 19 2024 19:02:23 UTC

GitHub Revision: eb776817a5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56458776725427632834749451790671712939002859133119076946547796163671543192855

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.640s	86.566us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.380s	79.276us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.610s	570.608us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.540s	337.864us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.720s	66.205us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.790s	15.719us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.350s	387.303us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.830s	15.306us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.690s	35.138us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.790s	15.719us	20	20	100.00
		gpio_csr_aliasing	0.830s	15.306us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.270s	148.033us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.500s	58.235us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	0.980s	56.961us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.540s	386.058us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.580s	130.006us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.650s	157.794us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	28.330s	544.850us	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.410s	576.506us	50	50	100.00
V2	full_random	gpio_full_random	1.120s	103.045us	50	50	100.00
V2	stress_all	gpio_stress_all	3.525m	108.550ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.660s	16.871us	50	50	100.00
V2	intr_test	gpio_intr_test	0.760s	24.100us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.130s	304.402us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.130s	304.402us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.790s	15.719us	20	20	100.00
		gpio_same_csr_outstanding	0.930s	18.866us	20	20	100.00
		gpio_csr_aliasing	0.830s	15.306us	5	5	100.00
		gpio_csr_hw_reset	0.720s	66.205us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.790s	15.719us	20	20	100.00
		gpio_same_csr_outstanding	0.930s	18.866us	20	20	100.00
		gpio_csr_aliasing	0.830s	15.306us	5	5	100.00
		gpio_csr_hw_reset	0.720s	66.205us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.550s	353.613us	20	20	100.00
		gpio_sec_cm	1.020s	367.728us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.550s	353.613us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	38.583m	399.442ms	24	50	48.00
V3		TOTAL			24	50	48.00
		TOTAL			944	970	97.32

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 26 failures:
  • Test gpio_stress_all_with_rand_reset has 26 failures.

    • 0.gpio_stress_all_with_rand_reset.77676300710304190342012514504451369449215380199754870374427791241011062440704
      Line 4735, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 64795550238 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 64795550238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.gpio_stress_all_with_rand_reset.85373414740703380389012428581299484038921278259592566893517120420233315746577
      Line 9094, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 195814858905 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 195814858905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 24 more failures.

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