GPIO Simulation Results

Tuesday May 21 2024 19:02:35 UTC

GitHub Revision: be3d980075

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85829748320245376283659198434338498577935164172956485671224275001047693479661

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.660s	92.761us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.670s	592.362us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.760s	216.782us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.610s	108.460us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.690s	33.722us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.670s	119.369us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.480s	376.711us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.850s	59.272us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.960s	154.606us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.670s	119.369us	20	20	100.00
		gpio_csr_aliasing	0.850s	59.272us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.540s	109.598us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.440s	79.023us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	1.060s	50.763us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.520s	343.123us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.800s	432.346us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	4.150s	97.267us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	28.300s	850.596us	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	8.070s	617.670us	50	50	100.00
V2	full_random	gpio_full_random	1.140s	92.252us	50	50	100.00
V2	stress_all	gpio_stress_all	4.220m	267.224ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.670s	17.143us	50	50	100.00
V2	intr_test	gpio_intr_test	0.650s	16.280us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	2.900s	612.450us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	2.900s	612.450us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.670s	119.369us	20	20	100.00
		gpio_same_csr_outstanding	0.940s	34.671us	20	20	100.00
		gpio_csr_aliasing	0.850s	59.272us	5	5	100.00
		gpio_csr_hw_reset	0.690s	33.722us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.670s	119.369us	20	20	100.00
		gpio_same_csr_outstanding	0.940s	34.671us	20	20	100.00
		gpio_csr_aliasing	0.850s	59.272us	5	5	100.00
		gpio_csr_hw_reset	0.690s	33.722us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.500s	672.752us	20	20	100.00
		gpio_sec_cm	1.010s	175.159us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.500s	672.752us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	41.029m	991.054ms	18	50	36.00
V3		TOTAL			18	50	36.00
		TOTAL			938	970	96.70

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 32 failures:
  • Test gpio_stress_all_with_rand_reset has 32 failures.

    • 0.gpio_stress_all_with_rand_reset.88710941415120405790099364663616036739004832475756235944649327572750863999500
      Line 255, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 657444488 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 657444488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.gpio_stress_all_with_rand_reset.42614706117166218808751178757342853971536784726937130465186715213485780991536
      Line 463, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/2.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2353498644 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2353498644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 30 more failures.

Past Results

• Latest
• lint
• 2024.05.20_03.51.18
• 2024.05.17_06.19.30
• 2024.05.15_02.48.10
• 2024.05.13_03.36.36
• 2024.05.10_04.23.23
• 2024.05.08_03.32.43