GPIO Simulation Results

Thursday June 27 2024 23:02:31 UTC

GitHub Revision: 8db2a18db1

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 100513533386727882033709335126269317053614297947080434367729937568368619502352

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.510s	351.875us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.480s	97.196us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.430s	81.724us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.500s	52.122us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.660s	106.312us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.780s	44.584us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.510s	770.114us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.910s	34.228us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.750s	154.423us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.780s	44.584us	20	20	100.00
		gpio_csr_aliasing	0.910s	34.228us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.490s	70.056us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.550s	137.644us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	1.010s	28.785us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.490s	218.051us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.420s	2.327ms	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.510s	348.060us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	28.140s	12.707ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.170s	604.792us	50	50	100.00
V2	full_random	gpio_full_random	1.250s	92.031us	50	50	100.00
V2	stress_all	gpio_stress_all	3.684m	33.736ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.680s	42.713us	50	50	100.00
V2	intr_test	gpio_intr_test	0.800s	62.553us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.230s	1.428ms	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.230s	1.428ms	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.780s	44.584us	20	20	100.00
		gpio_same_csr_outstanding	0.920s	191.777us	20	20	100.00
		gpio_csr_aliasing	0.910s	34.228us	5	5	100.00
		gpio_csr_hw_reset	0.660s	106.312us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.780s	44.584us	20	20	100.00
		gpio_same_csr_outstanding	0.920s	191.777us	20	20	100.00
		gpio_csr_aliasing	0.910s	34.228us	5	5	100.00
		gpio_csr_hw_reset	0.660s	106.312us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.550s	357.451us	20	20	100.00
		gpio_sec_cm	0.910s	636.266us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.550s	357.451us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	38.765m	119.882ms	26	50	52.00
V3		TOTAL			26	50	52.00
		TOTAL			946	970	97.53

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:
  • Test gpio_stress_all_with_rand_reset has 24 failures.

    • 1.gpio_stress_all_with_rand_reset.81816909979300116003359542786090184381146600746670347846483937329235725083849
      Line 426, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1395653800 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1395653800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.gpio_stress_all_with_rand_reset.35824313950432185752142420923863628107794726330715067235009522921350589578099
      Line 2181, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/3.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 10216808156 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 10216808156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 22 more failures.

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