GPIO Simulation Results

Wednesday June 26 2024 23:02:36 UTC

GitHub Revision: be1c4a4f52

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 44766564427213563291105655232733134394512207819884794315335669279596867428010

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.480s	317.376us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.400s	267.446us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.580s	89.300us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.750s	104.543us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.680s	28.284us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.680s	53.702us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	2.520s	504.657us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.890s	49.730us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.610s	63.940us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.680s	53.702us	20	20	100.00
		gpio_csr_aliasing	0.890s	49.730us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.380s	174.241us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.360s	100.233us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	0.930s	30.865us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.570s	1.197ms	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.770s	454.860us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.590s	189.790us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	27.670s	930.544us	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.360s	925.041us	50	50	100.00
V2	full_random	gpio_full_random	1.120s	1.327ms	50	50	100.00
V2	stress_all	gpio_stress_all	3.930m	120.539ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.620s	38.606us	50	50	100.00
V2	intr_test	gpio_intr_test	0.650s	13.947us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.440s	199.901us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.440s	199.901us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.680s	53.702us	20	20	100.00
		gpio_same_csr_outstanding	0.910s	43.327us	20	20	100.00
		gpio_csr_aliasing	0.890s	49.730us	5	5	100.00
		gpio_csr_hw_reset	0.680s	28.284us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.680s	53.702us	20	20	100.00
		gpio_same_csr_outstanding	0.910s	43.327us	20	20	100.00
		gpio_csr_aliasing	0.890s	49.730us	5	5	100.00
		gpio_csr_hw_reset	0.680s	28.284us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.470s	182.879us	20	20	100.00
		gpio_sec_cm	0.980s	90.231us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.470s	182.879us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	36.732m	94.866ms	17	50	34.00
V3		TOTAL			17	50	34.00
		TOTAL			937	970	96.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 33 failures:
  • Test gpio_stress_all_with_rand_reset has 33 failures.

    • 1.gpio_stress_all_with_rand_reset.55066201912750647416022034148827252860094459762382755221411290507204792055350
      Line 315, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 368759837 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 368759837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.gpio_stress_all_with_rand_reset.72043355377909225595922056572067842705324239972619219667603195207109490580120
      Line 448, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/2.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 642583341 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 642583341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 31 more failures.

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