GPIO Simulation Results

Friday June 28 2024 23:02:02 UTC

GitHub Revision: 3d5220a43f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 73442097946972310753089853920865571566707682704390544987111276126114608747389

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.570s	104.131us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.540s	344.572us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.500s	386.975us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.540s	316.092us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.660s	50.028us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.680s	49.759us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.070s	265.050us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.900s	31.513us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.520s	35.849us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.680s	49.759us	20	20	100.00
		gpio_csr_aliasing	0.900s	31.513us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.430s	108.824us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.390s	72.811us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	0.940s	161.836us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.530s	99.422us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.820s	239.853us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.960s	187.570us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	28.650s	942.517us	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	5.850s	547.741us	50	50	100.00
V2	full_random	gpio_full_random	1.130s	96.942us	50	50	100.00
V2	stress_all	gpio_stress_all	3.718m	35.273ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.640s	16.554us	50	50	100.00
V2	intr_test	gpio_intr_test	0.680s	20.348us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.330s	187.018us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.330s	187.018us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.680s	49.759us	20	20	100.00
		gpio_same_csr_outstanding	0.910s	22.495us	20	20	100.00
		gpio_csr_aliasing	0.900s	31.513us	5	5	100.00
		gpio_csr_hw_reset	0.660s	50.028us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.680s	49.759us	20	20	100.00
		gpio_same_csr_outstanding	0.910s	22.495us	20	20	100.00
		gpio_csr_aliasing	0.900s	31.513us	5	5	100.00
		gpio_csr_hw_reset	0.660s	50.028us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.470s	112.373us	20	20	100.00
		gpio_sec_cm	0.980s	809.660us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.470s	112.373us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	38.193m	216.850ms	18	50	36.00
V3		TOTAL			18	50	36.00
		TOTAL			938	970	96.70

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 32 failures:
  • Test gpio_stress_all_with_rand_reset has 32 failures.

    • 0.gpio_stress_all_with_rand_reset.1438455375340440632563130919873905850410773313141509373426711576250278740387
      Line 3237, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 28608972595 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 28608972595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.gpio_stress_all_with_rand_reset.24973547350783826805795733969019522635825320874777051390860216077427211265839
      Line 2860, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/2.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 50369481100 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 50369481100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 30 more failures.

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