GPIO Simulation Results

Sunday July 07 2024 23:02:38 UTC

GitHub Revision: `2e5d86c9b5`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75221189197949424635294305394615322888112457483844341597147780944629972574676

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.510s	352.045us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.520s	257.885us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.560s	361.040us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.700s	493.416us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.670s	22.654us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.670s	16.604us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.360s	926.763us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.890s	36.663us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.720s	36.782us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.670s	16.604us	20	20	100.00
		gpio_csr_aliasing	0.890s	36.663us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.430s	146.987us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.430s	60.699us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	1.010s	72.629us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.560s	90.621us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.880s	242.252us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.960s	1.739ms	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	27.490s	14.972ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.370s	581.318us	50	50	100.00
V2	full_random	gpio_full_random	1.110s	91.721us	50	50	100.00
V2	stress_all	gpio_stress_all	3.788m	58.201ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.630s	13.547us	50	50	100.00
V2	intr_test	gpio_intr_test	0.640s	18.331us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.170s	495.400us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.170s	495.400us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.670s	16.604us	20	20	100.00
		gpio_same_csr_outstanding	0.910s	132.500us	20	20	100.00
		gpio_csr_aliasing	0.890s	36.663us	5	5	100.00
		gpio_csr_hw_reset	0.670s	22.654us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.670s	16.604us	20	20	100.00
		gpio_same_csr_outstanding	0.910s	132.500us	20	20	100.00
		gpio_csr_aliasing	0.890s	36.663us	5	5	100.00
		gpio_csr_hw_reset	0.670s	22.654us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.610s	1.738ms	20	20	100.00
		gpio_sec_cm	1.000s	1.651ms	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.610s	1.738ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	43.393m	323.044ms	25	50	50.00
V3		TOTAL			25	50	50.00
		TOTAL			945	970	97.42

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 25 failures:
- Test gpio_stress_all_with_rand_reset has 25 failures.
  - 1.gpio_stress_all_with_rand_reset.60815958147040831285641086850480718712546767054278322098691427252220188302097
    Line 3019, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 17283874979 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 17283874979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.gpio_stress_all_with_rand_reset.74929354484842247757461674254798697587744072702633695302322626746804594166323
    Line 3918, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/2.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 65300282779 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 65300282779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 23 more failures.

GPIO Simulation Results

Sunday July 07 2024 23:02:38 UTC

GitHub Revision: 2e5d86c9b5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75221189197949424635294305394615322888112457483844341597147780944629972574676

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `2e5d86c9b5`