GPIO Simulation Results

Tuesday July 09 2024 23:02:48 UTC

GitHub Revision: `6a84251492`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 61727890964832844865465694323650730626175387240181955975848876152363892893427

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.540s	710.175us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.440s	259.103us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.600s	180.996us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.650s	64.869us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.690s	17.873us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.680s	11.812us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.070s	351.244us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.800s	31.331us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.680s	70.211us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.680s	11.812us	20	20	100.00
		gpio_csr_aliasing	0.800s	31.331us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.410s	281.436us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.380s	286.504us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	0.970s	50.518us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.500s	92.225us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.630s	791.548us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.760s	418.996us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	27.190s	1.049ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.560s	8.044ms	50	50	100.00
V2	full_random	gpio_full_random	1.070s	91.735us	50	50	100.00
V2	stress_all	gpio_stress_all	3.710m	63.297ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.640s	34.962us	50	50	100.00
V2	intr_test	gpio_intr_test	0.690s	13.798us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.740s	267.113us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.740s	267.113us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.680s	11.812us	20	20	100.00
		gpio_same_csr_outstanding	0.890s	120.892us	20	20	100.00
		gpio_csr_aliasing	0.800s	31.331us	5	5	100.00
		gpio_csr_hw_reset	0.690s	17.873us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.680s	11.812us	20	20	100.00
		gpio_same_csr_outstanding	0.890s	120.892us	20	20	100.00
		gpio_csr_aliasing	0.800s	31.331us	5	5	100.00
		gpio_csr_hw_reset	0.690s	17.873us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.570s	100.173us	20	20	100.00
		gpio_sec_cm	0.840s	81.177us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.570s	100.173us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	50.026m	253.398ms	26	50	52.00
V3		TOTAL			26	50	52.00
		TOTAL			946	970	97.53

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:825) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:
- Test gpio_stress_all_with_rand_reset has 24 failures.
  - 2.gpio_stress_all_with_rand_reset.38212716733771719085874521359738299321757091400728404495437619288007318822297
    Line 3236, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/2.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 28910228554 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 28910228554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.gpio_stress_all_with_rand_reset.11080137330175199374714056904458021818248111425043707732903306360613571848806
    Line 2692, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/4.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 18659529849 ps: (cip_base_vseq.sv:825) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 18659529849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 22 more failures.

GPIO Simulation Results

Tuesday July 09 2024 23:02:48 UTC

GitHub Revision: 6a84251492

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 61727890964832844865465694323650730626175387240181955975848876152363892893427

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `6a84251492`