GPIO Simulation Results

Wednesday July 10 2024 23:02:26 UTC

GitHub Revision: 39211701b5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 52262812535389540465251148247405743574935129745685597413714598750252192397067

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke gpio_smoke 1.550s 207.894us 50 50 100.00
gpio_smoke_no_pullup_pulldown 1.660s 322.374us 50 50 100.00
gpio_smoke_en_cdc_prim 1.550s 619.065us 50 50 100.00
gpio_smoke_no_pullup_pulldown_en_cdc_prim 1.600s 586.315us 50 50 100.00
V1 csr_hw_reset gpio_csr_hw_reset 0.690s 19.762us 5 5 100.00
V1 csr_rw gpio_csr_rw 0.690s 11.505us 20 20 100.00
V1 csr_bit_bash gpio_csr_bit_bash 3.680s 1.501ms 5 5 100.00
V1 csr_aliasing gpio_csr_aliasing 0.940s 299.265us 5 5 100.00
V1 csr_mem_rw_with_rand_reset gpio_csr_mem_rw_with_rand_reset 1.530s 135.885us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr gpio_csr_rw 0.690s 11.505us 20 20 100.00
gpio_csr_aliasing 0.940s 299.265us 5 5 100.00
V1 TOTAL 255 255 100.00
V2 direct_and_masked_out gpio_random_dout_din 1.530s 57.517us 50 50 100.00
gpio_random_dout_din_no_pullup_pulldown 1.430s 116.978us 50 50 100.00
V2 out_in_regs_read_write gpio_dout_din_regs_random_rw 0.980s 138.371us 50 50 100.00
V2 gpio_interrupt_programming gpio_intr_rand_pgm 1.570s 785.890us 50 50 100.00
V2 random_interrupt_trigger gpio_rand_intr_trigger 3.760s 112.532us 50 50 100.00
V2 interrupt_and_noise_filter gpio_intr_with_filter_rand_intr_event 3.990s 91.282us 50 50 100.00
V2 noise_filter_stress gpio_filter_stress 29.570s 540.436us 50 50 100.00
V2 regs_long_reads_and_writes gpio_random_long_reg_writes_reg_reads 7.210s 406.969us 50 50 100.00
V2 full_random gpio_full_random 1.200s 357.155us 50 50 100.00
V2 stress_all gpio_stress_all 3.833m 15.792ms 50 50 100.00
V2 alert_test gpio_alert_test 0.640s 16.514us 50 50 100.00
V2 intr_test gpio_intr_test 0.660s 45.270us 50 50 100.00
V2 tl_d_oob_addr_access gpio_tl_errors 3.560s 419.504us 20 20 100.00
V2 tl_d_illegal_access gpio_tl_errors 3.560s 419.504us 20 20 100.00
V2 tl_d_outstanding_access gpio_csr_rw 0.690s 11.505us 20 20 100.00
gpio_same_csr_outstanding 0.920s 20.680us 20 20 100.00
gpio_csr_aliasing 0.940s 299.265us 5 5 100.00
gpio_csr_hw_reset 0.690s 19.762us 5 5 100.00
V2 tl_d_partial_access gpio_csr_rw 0.690s 11.505us 20 20 100.00
gpio_same_csr_outstanding 0.920s 20.680us 20 20 100.00
gpio_csr_aliasing 0.940s 299.265us 5 5 100.00
gpio_csr_hw_reset 0.690s 19.762us 5 5 100.00
V2 TOTAL 640 640 100.00
V2S tl_intg_err gpio_tl_intg_err 1.500s 469.050us 20 20 100.00
gpio_sec_cm 0.940s 152.337us 5 5 100.00
V2S sec_cm_bus_integrity gpio_tl_intg_err 1.500s 469.050us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset gpio_stress_all_with_rand_reset 49.969m 1.861s 26 50 52.00
V3 TOTAL 26 50 52.00
TOTAL 946 970 97.53

Testplan Progress

Items Total Written Passing Progress
V1 9 9 9 100.00
V2 14 14 14 100.00
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.63 99.06 99.24 100.00 -- 99.80 99.68 99.99

Failure Buckets

Past Results