GPIO Simulation Results

Friday October 11 2024 20:19:09 UTC

GitHub Revision: 8a1401d614

Branch: os_regression_2024_10_11

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 53663846044628477120113920685171085698887397097422685916033931805982305505364

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke gpio_smoke 2.140s 162.419us 50 50 100.00
gpio_smoke_no_pullup_pulldown 2.290s 95.049us 50 50 100.00
gpio_smoke_en_cdc_prim 2.390s 95.768us 50 50 100.00
gpio_smoke_no_pullup_pulldown_en_cdc_prim 2.260s 84.062us 50 50 100.00
V1 csr_hw_reset gpio_csr_hw_reset 0.700s 21.343us 5 5 100.00
V1 csr_rw gpio_csr_rw 54.416s 17 20 85.00
V1 csr_bit_bash gpio_csr_bit_bash 2.810s 152.114us 5 5 100.00
V1 csr_aliasing gpio_csr_aliasing 0.820s 32.777us 5 5 100.00
V1 csr_mem_rw_with_rand_reset gpio_csr_mem_rw_with_rand_reset 54.348s 15 20 75.00
V1 regwen_csr_and_corresponding_lockable_csr gpio_csr_rw 54.416s 17 20 85.00
gpio_csr_aliasing 0.820s 32.777us 5 5 100.00
V1 TOTAL 247 255 96.86
V2 direct_and_masked_out gpio_random_dout_din 2.080s 64.271us 50 50 100.00
gpio_random_dout_din_no_pullup_pulldown 1.920s 508.026us 50 50 100.00
V2 out_in_regs_read_write gpio_dout_din_regs_random_rw 1.520s 46.893us 50 50 100.00
V2 gpio_interrupt_programming gpio_intr_rand_pgm 2.210s 187.953us 50 50 100.00
V2 random_interrupt_trigger gpio_rand_intr_trigger 5.380s 1.446ms 50 50 100.00
V2 interrupt_and_noise_filter gpio_intr_with_filter_rand_intr_event 5.280s 354.631us 50 50 100.00
V2 noise_filter_stress gpio_filter_stress 30.410s 1.058ms 50 50 100.00
V2 regs_long_reads_and_writes gpio_random_long_reg_writes_reg_reads 7.760s 253.655us 50 50 100.00
V2 full_random gpio_full_random 1.630s 546.005us 50 50 100.00
V2 stress_all gpio_stress_all 4.521m 34.670ms 50 50 100.00
V2 alert_test gpio_alert_test 0.910s 29.066us 50 50 100.00
V2 intr_test gpio_intr_test 54.246s 39 50 78.00
V2 tl_d_oob_addr_access gpio_tl_errors 54.273s 18 20 90.00
V2 tl_d_illegal_access gpio_tl_errors 54.273s 18 20 90.00
V2 tl_d_outstanding_access gpio_csr_rw 54.416s 17 20 85.00
gpio_same_csr_outstanding 41.224s 16 20 80.00
gpio_csr_aliasing 0.820s 32.777us 5 5 100.00
gpio_csr_hw_reset 0.700s 21.343us 5 5 100.00
V2 tl_d_partial_access gpio_csr_rw 54.416s 17 20 85.00
gpio_same_csr_outstanding 41.224s 16 20 80.00
gpio_csr_aliasing 0.820s 32.777us 5 5 100.00
gpio_csr_hw_reset 0.700s 21.343us 5 5 100.00
V2 TOTAL 623 640 97.34
V2S tl_intg_err gpio_tl_intg_err 47.339s 19 20 95.00
gpio_sec_cm 1.030s 97.533us 5 5 100.00
V2S sec_cm_bus_integrity gpio_tl_intg_err 47.339s 19 20 95.00
V2S TOTAL 24 25 96.00
V3 stress_all_with_rand_reset gpio_stress_all_with_rand_reset 3.032m 5.628ms 19 50 38.00
V3 TOTAL 19 50 38.00
TOTAL 913 970 94.12

Testplan Progress

Items Total Written Passing Progress
V1 9 9 7 77.78
V2 14 14 11 78.57
V2S 2 2 1 50.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.62 99.04 99.24 100.00 -- 99.80 99.68 99.99

Failure Buckets

Past Results