GPIO Simulation Results

Wednesday September 18 2024 00:48:27 UTC

GitHub Revision: 7e34e67ade

Branch: os_regression_2024_09_17

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 4190660412037082522497784440658734031572790705268868319466386425736861254975

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.980s	272.861us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	2.220s	53.927us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.800s	82.038us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.870s	77.623us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.950s	17.364us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.930s	20.314us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	4.180s	1.256ms	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	1.110s	27.363us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	2.200s	59.333us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.930s	20.314us	20	20	100.00
		gpio_csr_aliasing	1.110s	27.363us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	2.060s	71.466us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.870s	36.695us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	1.430s	213.799us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	2.410s	97.518us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	5.190s	651.083us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	5.320s	87.612us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	31.170s	1.778ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	8.190s	4.299ms	50	50	100.00
V2	full_random	gpio_full_random	1.610s	470.781us	50	50	100.00
V2	stress_all	gpio_stress_all	3.655m	31.418ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.910s	14.020us	50	50	100.00
V2	intr_test	gpio_intr_test	0.950s	14.501us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.220s	826.306us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.220s	826.306us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.930s	20.314us	20	20	100.00
		gpio_same_csr_outstanding	1.320s	42.203us	20	20	100.00
		gpio_csr_aliasing	1.110s	27.363us	5	5	100.00
		gpio_csr_hw_reset	0.950s	17.364us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.930s	20.314us	20	20	100.00
		gpio_same_csr_outstanding	1.320s	42.203us	20	20	100.00
		gpio_csr_aliasing	1.110s	27.363us	5	5	100.00
		gpio_csr_hw_reset	0.950s	17.364us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.890s	273.831us	20	20	100.00
		gpio_sec_cm	1.400s	185.205us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.890s	273.831us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	4.086m	29.432ms	21	50	42.00
V3		TOTAL			21	50	42.00
		TOTAL			941	970	97.01

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.62	99.04	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:867) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 29 failures:
  • Test gpio_stress_all_with_rand_reset has 29 failures.

    • 2.gpio_stress_all_with_rand_reset.101189169136197617473868891095957721438204246879367003806739267263148062483204
      Line 479, in log /workspaces/repo/scratch/os_regression_2024_09_17/gpio-sim-vcs/2.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1654729663 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1654729663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.gpio_stress_all_with_rand_reset.11664231321413601531894790905061972345363028248652936793024710402244644676209
      Line 858, in log /workspaces/repo/scratch/os_regression_2024_09_17/gpio-sim-vcs/3.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3620566277 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3620566277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 27 more failures.

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