GPIO Simulation Results

Wednesday October 02 2024 15:31:08 UTC

GitHub Revision: 1cb1c3d135

Branch: os_regression_2024_10_02

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 110153111371602750214979040795005912991145924440069071731765206333111748946968

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	2.250s	104.685us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	2.180s	220.245us	50	50	100.00
		gpio_smoke_en_cdc_prim	2.060s	96.517us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.920s	90.109us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	1.040s	65.348us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.970s	15.638us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.160s	143.504us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	1.380s	221.792us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	2.560s	56.932us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.970s	15.638us	20	20	100.00
		gpio_csr_aliasing	1.380s	221.792us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	2.160s	58.523us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.970s	249.574us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	1.470s	161.400us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	2.410s	1.820ms	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	5.000s	465.421us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	4.760s	404.322us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	34.860s	2.230ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	9.200s	1.984ms	50	50	100.00
V2	full_random	gpio_full_random	1.700s	78.131us	50	50	100.00
V2	stress_all	gpio_stress_all	4.775m	325.896ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.930s	25.670us	50	50	100.00
V2	intr_test	gpio_intr_test	0.950s	14.579us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	4.060s	94.846us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	4.060s	94.846us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.970s	15.638us	20	20	100.00
		gpio_same_csr_outstanding	1.370s	37.406us	20	20	100.00
		gpio_csr_aliasing	1.380s	221.792us	5	5	100.00
		gpio_csr_hw_reset	1.040s	65.348us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.970s	15.638us	20	20	100.00
		gpio_same_csr_outstanding	1.370s	37.406us	20	20	100.00
		gpio_csr_aliasing	1.380s	221.792us	5	5	100.00
		gpio_csr_hw_reset	1.040s	65.348us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	2.240s	494.929us	20	20	100.00
		gpio_sec_cm	0.880s	326.198us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	2.240s	494.929us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	3.562m	5.468ms	21	50	42.00
V3		TOTAL			21	50	42.00
		TOTAL			941	970	97.01

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.62	99.04	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:867) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 29 failures:
  • Test gpio_stress_all_with_rand_reset has 29 failures.

    • 0.gpio_stress_all_with_rand_reset.79104901407029600615909161936131135791446500001570717058291614563251616054162
      Line 289, in log /workspaces/repo/scratch/os_regression_2024_10_02/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 427083873 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 427083873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.gpio_stress_all_with_rand_reset.97057271181195981130883012299226994319129765938699046384645521736811091693731
      Line 299, in log /workspaces/repo/scratch/os_regression_2024_10_02/gpio-sim-vcs/2.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3094429875 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3094429875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 27 more failures.

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