GPIO Simulation Results

Wednesday October 09 2024 01:12:40 UTC

GitHub Revision: `29d22a60a2`

Branch: os_regression_2024_10_08

Simulator: VCS

Build randomization enabled with --build-seed 53714374671147886608112573291731904665579606104149618024735414983036052389689

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	2.170s	72.976us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	2.200s	51.498us	50	50	100.00
		gpio_smoke_en_cdc_prim	49.864s		49	50	98.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	49.859s		49	50	98.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.660s	31.479us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.640s	12.235us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	2.800s	746.141us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.850s	18.513us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	0.980s	146.210us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.640s	12.235us	20	20	100.00
		gpio_csr_aliasing	0.850s	18.513us	5	5	100.00
V1		TOTAL			253	255	99.22
V2	direct_and_masked_out	gpio_random_dout_din	2.170s	131.698us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	2.120s	259.257us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	1.370s	49.877us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	2.360s	369.101us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	5.570s	123.869us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	5.290s	490.100us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	34.210s	992.284us	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	9.010s	566.586us	50	50	100.00
V2	full_random	gpio_full_random	1.860s	109.317us	50	50	100.00
V2	stress_all	gpio_stress_all	3.994m	14.898ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.930s	13.891us	50	50	100.00
V2	intr_test	gpio_intr_test	26.982s		49	50	98.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.250s	218.822us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.250s	218.822us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.640s	12.235us	20	20	100.00
		gpio_same_csr_outstanding	0.860s	44.472us	20	20	100.00
		gpio_csr_aliasing	0.850s	18.513us	5	5	100.00
		gpio_csr_hw_reset	0.660s	31.479us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.640s	12.235us	20	20	100.00
		gpio_same_csr_outstanding	0.860s	44.472us	20	20	100.00
		gpio_csr_aliasing	0.850s	18.513us	5	5	100.00
		gpio_csr_hw_reset	0.660s	31.479us	5	5	100.00
V2		TOTAL			639	640	99.84
V2S	tl_intg_err	gpio_tl_intg_err	1.480s	122.829us	20	20	100.00
		gpio_sec_cm	1.560s	387.724us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.480s	122.829us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	3.245m	11.133ms	15	50	30.00
V3		TOTAL			15	50	30.00
		TOTAL			932	970	96.08

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	7	77.78
V2	14	14	13	92.86
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.62	99.04	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:867) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 35 failures:
- Test gpio_stress_all_with_rand_reset has 35 failures.
  - 0.gpio_stress_all_with_rand_reset.7810045359927763048957545000026858092386233810688544394651140738038719365811
    Line 754, in log /workspaces/repo/scratch/os_regression_2024_10_08/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8554237327 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 8554237327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.gpio_stress_all_with_rand_reset.29740322703891018792565605269211764048941180011618864284761021814912217161215
    Line 461, in log /workspaces/repo/scratch/os_regression_2024_10_08/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 12688955838 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 12688955838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 33 more failures.

Job returned non-zero exit code has 3 failures:

Test gpio_smoke_no_pullup_pulldown_en_cdc_prim has 1 failures.

14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.26666500770751430935251030693799009670133486164106340627043825396622790419841
Log /workspaces/repo/scratch/os_regression_2024_10_08/gpio-sim-vcs/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Oct  9 06:06 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

Test gpio_smoke_en_cdc_prim has 1 failures.

15.gpio_smoke_en_cdc_prim.34210110849165970601953305194543406279786354228441117715384845689237711382124
Log /workspaces/repo/scratch/os_regression_2024_10_08/gpio-sim-vcs/15.gpio_smoke_en_cdc_prim/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Oct  9 06:06 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

Test gpio_intr_test has 1 failures.

33.gpio_intr_test.72646148540667851882894092084001982329190886921326029350942600111532293949367
Log /workspaces/repo/scratch/os_regression_2024_10_08/gpio-sim-vcs/33.gpio_intr_test/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Oct  9 06:06 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255