HMAC Simulation Results

Friday May 26 2023 07:06:59 UTC

GitHub Revision: `213e792ea`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2340441291

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	4.770s	764.387us	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.760s	19.439us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.760s	25.513us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	7.970s	807.543us	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	2.580s	164.766us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	12.997m	367.548ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.760s	25.513us	20	20	100.00
		hmac_csr_aliasing	2.580s	164.766us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	1.923m	38.010ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.124m	37.008ms	50	50	100.00
V2	test_vectors	hmac_test_sha_vectors	8.333m	44.575ms	47	50	94.00
		hmac_test_hmac_vectors	1.240s	248.482us	50	50	100.00
V2	burst_wr	hmac_burst_wr	54.570s	5.871ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	2.519m	26.829ms	50	50	100.00
V2	error	hmac_error	3.637m	69.333ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	1.741m	22.962ms	50	50	100.00
V2	stress_all	hmac_stress_all	43.160m	392.703ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.630s	16.087us	50	50	100.00
V2	intr_test	hmac_intr_test	0.670s	27.776us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	3.550s	232.881us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	3.550s	232.881us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.760s	19.439us	5	5	100.00
		hmac_csr_rw	0.760s	25.513us	20	20	100.00
		hmac_csr_aliasing	2.580s	164.766us	5	5	100.00
		hmac_same_csr_outstanding	1.470s	75.496us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.760s	19.439us	5	5	100.00
		hmac_csr_rw	0.760s	25.513us	20	20	100.00
		hmac_csr_aliasing	2.580s	164.766us	5	5	100.00
		hmac_same_csr_outstanding	1.470s	75.496us	20	20	100.00
V2		TOTAL			587	590	99.49
V2S	tl_intg_err	hmac_sec_cm	0.970s	91.524us	5	5	100.00
		hmac_tl_intg_err	2.600s	693.857us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	2.600s	693.857us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	4.770s	764.387us	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	1.777h	638.842ms	195	200	97.50
V3		TOTAL			195	200	97.50
		TOTAL			912	920	99.13

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	13	13	12	92.31
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.59	99.54	98.47	100.00	100.00	99.76	99.49	99.86

Failure Buckets

UVM_ERROR (hmac_base_vseq.sv:37) [hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 4 failures:

Test hmac_stress_all_with_rand_reset has 4 failures.

9.hmac_stress_all_with_rand_reset.1860715427
Line 502, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/9.hmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 16231548173 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 16231548173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

124.hmac_stress_all_with_rand_reset.3646839060
Line 746, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/124.hmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 39055758436 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 39055758436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:

Test hmac_test_sha_vectors has 3 failures.

20.hmac_test_sha_vectors.111044012
Line 215, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/20.hmac_test_sha_vectors/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

26.hmac_test_sha_vectors.2428817517
Line 215, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/26.hmac_test_sha_vectors/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (hmac_base_vseq.sv:37) [hmac_test_vectors_hmac_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 96.hmac_stress_all_with_rand_reset.3727756256
    Line 219, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/96.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @   2143737 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_test_vectors_hmac_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @   2143737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```