042415198f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | hmac_smoke | 4.620s | 923.932us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | hmac_csr_hw_reset | 0.690s | 93.460us | 4 | 5 | 80.00 |
| V1 | csr_rw | hmac_csr_rw | 0.740s | 27.325us | 18 | 20 | 90.00 |
| V1 | csr_bit_bash | hmac_csr_bit_bash | 9.160s | 4.055ms | 3 | 5 | 60.00 |
| V1 | csr_aliasing | hmac_csr_aliasing | 2.670s | 461.489us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | hmac_csr_mem_rw_with_rand_reset | 2.780s | 36.115us | 15 | 20 | 75.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | hmac_csr_rw | 0.740s | 27.325us | 18 | 20 | 90.00 |
| hmac_csr_aliasing | 2.670s | 461.489us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 95 | 105 | 90.48 | |||
| V2 | long_msg | hmac_long_msg | 2.299m | 8.263ms | 50 | 50 | 100.00 |
| V2 | back_pressure | hmac_back_pressure | 1.043m | 13.493ms | 50 | 50 | 100.00 |
| V2 | test_vectors | hmac_test_sha_vectors | 8.429m | 94.954ms | 44 | 50 | 88.00 |
| hmac_test_hmac_vectors | 1.220s | 71.311us | 50 | 50 | 100.00 | ||
| V2 | burst_wr | hmac_burst_wr | 1.328m | 1.688ms | 50 | 50 | 100.00 |
| V2 | datapath_stress | hmac_datapath_stress | 2.231m | 26.036ms | 50 | 50 | 100.00 |
| V2 | error | hmac_error | 3.715m | 19.015ms | 50 | 50 | 100.00 |
| V2 | wipe_secret | hmac_wipe_secret | 1.508m | 6.594ms | 50 | 50 | 100.00 |
| V2 | stress_all | hmac_stress_all | 33.747m | 735.665ms | 50 | 50 | 100.00 |
| V2 | alert_test | hmac_alert_test | 0.630s | 19.142us | 50 | 50 | 100.00 |
| V2 | intr_test | hmac_intr_test | 0.610s | 13.160us | 45 | 50 | 90.00 |
| V2 | tl_d_oob_addr_access | hmac_tl_errors | 3.200s | 240.183us | 17 | 20 | 85.00 |
| V2 | tl_d_illegal_access | hmac_tl_errors | 3.200s | 240.183us | 17 | 20 | 85.00 |
| V2 | tl_d_outstanding_access | hmac_csr_hw_reset | 0.690s | 93.460us | 4 | 5 | 80.00 |
| hmac_csr_rw | 0.740s | 27.325us | 18 | 20 | 90.00 | ||
| hmac_csr_aliasing | 2.670s | 461.489us | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 1.340s | 66.304us | 16 | 20 | 80.00 | ||
| V2 | tl_d_partial_access | hmac_csr_hw_reset | 0.690s | 93.460us | 4 | 5 | 80.00 |
| hmac_csr_rw | 0.740s | 27.325us | 18 | 20 | 90.00 | ||
| hmac_csr_aliasing | 2.670s | 461.489us | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 1.340s | 66.304us | 16 | 20 | 80.00 | ||
| V2 | TOTAL | 572 | 590 | 96.95 | |||
| V2S | tl_intg_err | hmac_sec_cm | 0.970s | 153.862us | 5 | 5 | 100.00 |
| hmac_tl_intg_err | 2.440s | 173.036us | 17 | 20 | 85.00 | ||
| V2S | sec_cm_bus_integrity | hmac_tl_intg_err | 2.440s | 173.036us | 17 | 20 | 85.00 |
| V2S | TOTAL | 22 | 25 | 88.00 | |||
| V3 | write_config_and_secret_key_during_msg_wr | hmac_smoke | 4.620s | 923.932us | 50 | 50 | 100.00 |
| V3 | stress_all_with_rand_reset | hmac_stress_all_with_rand_reset | 1.595h | 235.515ms | 191 | 200 | 95.50 |
| V3 | TOTAL | 191 | 200 | 95.50 | |||
| TOTAL | 880 | 920 | 95.65 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 2 | 33.33 |
| V2 | 13 | 13 | 9 | 69.23 |
| V2S | 2 | 2 | 1 | 50.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.62 | 99.53 | 98.69 | 100.00 | 100.00 | 99.76 | 99.49 | 99.86 |
Exit reason: Error: User command failed Job returned non-zero exit code has 25 failures:
Test hmac_csr_mem_rw_with_rand_reset has 5 failures.
0.hmac_csr_mem_rw_with_rand_reset.114130007939092249664386660917983847594518172439015907937336377912620680904096
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_csr_mem_rw_with_rand_reset/latest/run.log
[make]: simulate
cd /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest && /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95583648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.95583648
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:38 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
7.hmac_csr_mem_rw_with_rand_reset.2012626956720997617164788161718631436746841889214371635428546356927238520289
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/7.hmac_csr_mem_rw_with_rand_reset/latest/run.log
[make]: simulate
cd /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest && /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645573089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.2645573089
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:39 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 3 more failures.
Test hmac_intr_test has 5 failures.
2.hmac_intr_test.18637439511040995213345892072247784637264762781786945267444666208947510483231
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_intr_test/latest/run.log
[make]: simulate
cd /workspace/2.hmac_intr_test/latest && /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910282527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.1910282527
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:39 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
14.hmac_intr_test.113552878130588517650303014344663401688262670012566850523746134258570503231646
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/14.hmac_intr_test/latest/run.log
[make]: simulate
cd /workspace/14.hmac_intr_test/latest && /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133694622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.2133694622
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:38 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 3 more failures.
Test hmac_csr_bit_bash has 2 failures.
3.hmac_csr_bit_bash.113304685995069847030387121031149275188227372731891215783136554663989220244436
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/3.hmac_csr_bit_bash/latest/run.log
[make]: simulate
cd /workspace/3.hmac_csr_bit_bash/latest && /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870063572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.3870063572
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:38 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
4.hmac_csr_bit_bash.59863591144962159281824107526631884009785909673440005658188604667369035289721
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/4.hmac_csr_bit_bash/latest/run.log
[make]: simulate
cd /workspace/4.hmac_csr_bit_bash/latest && /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72242297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.72242297
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:39 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test hmac_tl_errors has 3 failures.
4.hmac_tl_errors.101163361487144501786495679291437840405396986990853698159501634899310543303169
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/4.hmac_tl_errors/latest/run.log
[make]: simulate
cd /workspace/4.hmac_tl_errors/latest && /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133258753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.2133258753
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:38 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
7.hmac_tl_errors.86649075845463310925172328594911276683870433583166623461664902548133100660305
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/7.hmac_tl_errors/latest/run.log
[make]: simulate
cd /workspace/7.hmac_tl_errors/latest && /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534235217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.3534235217
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:38 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 1 more failures.
Test hmac_csr_hw_reset has 1 failures.
4.hmac_csr_hw_reset.92762369380985338418299029757089236237077851762886784008733647944732386805095
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/4.hmac_csr_hw_reset/latest/run.log
[make]: simulate
cd /workspace/4.hmac_csr_hw_reset/latest && /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595847015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.3595847015
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:38 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 3 more tests.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 6 failures:
4.hmac_test_sha_vectors.111204641915400388438102194485981887653875005486949850823491733422923282761648
Line 248, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/4.hmac_test_sha_vectors/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.hmac_test_sha_vectors.13887152112897792480646978307720360704506500080138490374573269821369880547915
Line 248, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/11.hmac_test_sha_vectors/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_ERROR (hmac_base_vseq.sv:37) [hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 5 failures:
62.hmac_stress_all_with_rand_reset.58649358881547348495526606513664416453508446737934457371803820699094646881025
Line 258, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/62.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 9460062 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 9460062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
101.hmac_stress_all_with_rand_reset.63362485084648088477800646841849751971117306696164543503998452839925479545267
Line 457, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/101.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 14197605367 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 14197605367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (hmac_base_vseq.sv:37) [hmac_common_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
7.hmac_stress_all_with_rand_reset.82822950831907472437495651876436444741138514855256313194972044662184340231026
Line 710, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/7.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 43788903073 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 43788903073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (hmac_base_vseq.sv:37) [hmac_error_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
54.hmac_stress_all_with_rand_reset.50473616684668872317141457213566140284728155527657864952126118515805297307415
Line 1017, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/54.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 114195310187 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 114195310187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (hmac_base_vseq.sv:37) [hmac_test_vectors_hmac_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
137.hmac_stress_all_with_rand_reset.56986456924682912525548529202239781948081802672912892313215919580844559365405
Line 304, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/137.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3248397116 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_test_vectors_hmac_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 3248397116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (hmac_base_vseq.sv:37) [hmac_datapath_stress_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
143.hmac_stress_all_with_rand_reset.20163382665000580104770456536189319109568553464367380508700952603909402807737
Line 252, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/143.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1758957 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_datapath_stress_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1758957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---