cf38c1d296| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | hmac_smoke | 4.980s | 484.475us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | hmac_csr_hw_reset | 0.710s | 46.401us | 3 | 5 | 60.00 |
| V1 | csr_rw | hmac_csr_rw | 0.710s | 78.128us | 10 | 20 | 50.00 |
| V1 | csr_bit_bash | hmac_csr_bit_bash | 5.520s | 594.047us | 2 | 5 | 40.00 |
| V1 | csr_aliasing | hmac_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | hmac_csr_mem_rw_with_rand_reset | 2.630s | 36.842us | 14 | 20 | 70.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | hmac_csr_rw | 0.710s | 78.128us | 10 | 20 | 50.00 |
| hmac_csr_aliasing | 0 | 5 | 0.00 | ||||
| V1 | TOTAL | 79 | 105 | 75.24 | |||
| V2 | long_msg | hmac_long_msg | 2.012m | 67.520ms | 50 | 50 | 100.00 |
| V2 | back_pressure | hmac_back_pressure | 53.420s | 3.130ms | 50 | 50 | 100.00 |
| V2 | test_vectors | hmac_test_sha_vectors | 8.281m | 88.459ms | 47 | 50 | 94.00 |
| hmac_test_hmac_vectors | 1.240s | 217.065us | 50 | 50 | 100.00 | ||
| V2 | burst_wr | hmac_burst_wr | 58.260s | 2.662ms | 50 | 50 | 100.00 |
| V2 | datapath_stress | hmac_datapath_stress | 2.581m | 3.048ms | 50 | 50 | 100.00 |
| V2 | error | hmac_error | 3.914m | 17.953ms | 50 | 50 | 100.00 |
| V2 | wipe_secret | hmac_wipe_secret | 1.450m | 28.955ms | 50 | 50 | 100.00 |
| V2 | stress_all | hmac_stress_all | 39.314m | 61.157ms | 50 | 50 | 100.00 |
| V2 | alert_test | hmac_alert_test | 0.630s | 76.041us | 50 | 50 | 100.00 |
| V2 | intr_test | hmac_intr_test | 0.630s | 86.083us | 43 | 50 | 86.00 |
| V2 | tl_d_oob_addr_access | hmac_tl_errors | 3.240s | 1.211ms | 6 | 20 | 30.00 |
| V2 | tl_d_illegal_access | hmac_tl_errors | 3.240s | 1.211ms | 6 | 20 | 30.00 |
| V2 | tl_d_outstanding_access | hmac_csr_hw_reset | 0.710s | 46.401us | 3 | 5 | 60.00 |
| hmac_csr_rw | 0.710s | 78.128us | 10 | 20 | 50.00 | ||
| hmac_csr_aliasing | 0 | 5 | 0.00 | ||||
| hmac_same_csr_outstanding | 1.360s | 124.720us | 13 | 20 | 65.00 | ||
| V2 | tl_d_partial_access | hmac_csr_hw_reset | 0.710s | 46.401us | 3 | 5 | 60.00 |
| hmac_csr_rw | 0.710s | 78.128us | 10 | 20 | 50.00 | ||
| hmac_csr_aliasing | 0 | 5 | 0.00 | ||||
| hmac_same_csr_outstanding | 1.360s | 124.720us | 13 | 20 | 65.00 | ||
| V2 | TOTAL | 559 | 590 | 94.75 | |||
| V2S | tl_intg_err | hmac_sec_cm | 0.970s | 339.617us | 5 | 5 | 100.00 |
| hmac_tl_intg_err | 2.450s | 171.465us | 14 | 20 | 70.00 | ||
| V2S | sec_cm_bus_integrity | hmac_tl_intg_err | 2.450s | 171.465us | 14 | 20 | 70.00 |
| V2S | TOTAL | 19 | 25 | 76.00 | |||
| V3 | write_config_and_secret_key_during_msg_wr | hmac_smoke | 4.980s | 484.475us | 50 | 50 | 100.00 |
| V3 | stress_all_with_rand_reset | hmac_stress_all_with_rand_reset | 1.511h | 557.473ms | 192 | 200 | 96.00 |
| V3 | TOTAL | 192 | 200 | 96.00 | |||
| TOTAL | 849 | 920 | 92.28 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 1 | 16.67 |
| V2 | 13 | 13 | 9 | 69.23 |
| V2S | 2 | 2 | 1 | 50.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.59 | 99.53 | 98.47 | 100.00 | 100.00 | 99.76 | 99.49 | 99.86 |
Exit reason: Error: User command failed Job returned non-zero exit code has 60 failures:
Test hmac_csr_hw_reset has 2 failures.
0.hmac_csr_hw_reset.19561182296625655479087097866297691410914004804804907401659343146787059092115
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_csr_hw_reset/latest/run.log
[make]: simulate
cd /workspace/0.hmac_csr_hw_reset/latest && /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135930515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.4135930515
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 12:59 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
1.hmac_csr_hw_reset.43785172684273403226041814403492704018802175647286765695003435792133238241846
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_csr_hw_reset/latest/run.log
[make]: simulate
cd /workspace/1.hmac_csr_hw_reset/latest && /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226783286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.1226783286
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 12:59 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test hmac_csr_rw has 10 failures.
0.hmac_csr_rw.13834737317189685541335626009722386669786562718895375554302590833331563542616
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_csr_rw/latest/run.log
[make]: simulate
cd /workspace/0.hmac_csr_rw/latest && /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391160920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.2391160920
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 12:59 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
1.hmac_csr_rw.2521009931707503527657368023352526281176288677117585034153459604503961642516
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_csr_rw/latest/run.log
[make]: simulate
cd /workspace/1.hmac_csr_rw/latest && /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221699092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.1221699092
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 12:59 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 8 more failures.
Test hmac_csr_aliasing has 5 failures.
0.hmac_csr_aliasing.59550643442871813514701986925663085376871130869109119911009074574711049923452
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_csr_aliasing/latest/run.log
[make]: simulate
cd /workspace/0.hmac_csr_aliasing/latest && /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131367804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.4131367804
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 12:59 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
1.hmac_csr_aliasing.69032186338856579112192420280382740340540095795252027516111358360479845904185
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_csr_aliasing/latest/run.log
[make]: simulate
cd /workspace/1.hmac_csr_aliasing/latest && /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560421689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.2560421689
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 12:59 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 3 more failures.
Test hmac_same_csr_outstanding has 7 failures.
0.hmac_same_csr_outstanding.79676114492294933068890847299030799577777696857539698428096013799474472098852
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_same_csr_outstanding/latest/run.log
[make]: simulate
cd /workspace/0.hmac_same_csr_outstanding/latest && /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822025252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr_outstanding.822025252
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 12:59 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
6.hmac_same_csr_outstanding.22001102909770758317134492610265268141878644303790808728685443571655940350123
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/6.hmac_same_csr_outstanding/latest/run.log
[make]: simulate
cd /workspace/6.hmac_same_csr_outstanding/latest && /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267024555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr_outstanding.4267024555
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 12:59 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 5 more failures.
Test hmac_tl_errors has 14 failures.
1.hmac_tl_errors.49355976337126837716099969755576588496172170214340529109716623964249791349555
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_tl_errors/latest/run.log
[make]: simulate
cd /workspace/1.hmac_tl_errors/latest && /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741032755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.741032755
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 12:59 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
2.hmac_tl_errors.22897551708230227989034820088535787682442137748097841403435562923571945814136
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_tl_errors/latest/run.log
[make]: simulate
cd /workspace/2.hmac_tl_errors/latest && /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263679608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.1263679608
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 10 12:59 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 12 more failures.
... and 4 more tests.
UVM_ERROR (hmac_base_vseq.sv:37) [hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 4 failures:
23.hmac_stress_all_with_rand_reset.44150317914413303390018095008763462450193590478655795585640755130628529003759
Line 442, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/23.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 11159078114 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 11159078114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
40.hmac_stress_all_with_rand_reset.107199311098254545359549081156547230173377419728486935611508941725775877844281
Line 1465, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/40.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 51854383209 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 51854383209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
4.hmac_test_sha_vectors.72880141351535146409434406044397417459519962414592560929895453769112602844919
Line 248, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/4.hmac_test_sha_vectors/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.hmac_test_sha_vectors.48654469404584461703652057765438729713806080069875046937655898680234698339707
Line 248, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/9.hmac_test_sha_vectors/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (hmac_base_vseq.sv:37) [hmac_wipe_secret_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 2 failures:
1.hmac_stress_all_with_rand_reset.54286653131721105002052654566116248854661849802620483555017903427298642414467
Line 488, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 16666237807 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_wipe_secret_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 16666237807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
70.hmac_stress_all_with_rand_reset.29612316458748914821479353815886483988203950277110460968299356218044196891667
Line 313, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/70.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5968749155 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_wipe_secret_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 5968749155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (hmac_base_vseq.sv:37) [hmac_error_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
78.hmac_stress_all_with_rand_reset.92937334223608434006659065474773247544554093034147757887995529766227610844445
Line 560, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/78.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 63215895390 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 63215895390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (hmac_base_vseq.sv:37) [hmac_test_vectors_hmac_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
180.hmac_stress_all_with_rand_reset.85391356998769431624715889402376533403072921507990182117852487607325398018774
Line 1220, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/180.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 306729686204 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_test_vectors_hmac_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 306729686204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---