HMAC Simulation Results

Sunday January 14 2024 20:02:50 UTC

GitHub Revision: `5f48fbc0e7`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 17974844803940076144755676589184454804069451770040436570888369542024131598097

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	4.700s	448.016us	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.730s	79.330us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.780s	24.080us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	8.160s	197.394us	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	2.640s	136.888us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	14.718m	403.852ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.780s	24.080us	20	20	100.00
		hmac_csr_aliasing	2.640s	136.888us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	2.117m	7.472ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.168m	5.855ms	50	50	100.00
V2	test_vectors	hmac_test_sha_vectors	8.442m	120.569ms	48	50	96.00
		hmac_test_hmac_vectors	1.220s	133.986us	50	50	100.00
V2	burst_wr	hmac_burst_wr	1.158m	1.512ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	2.408m	2.873ms	50	50	100.00
V2	error	hmac_error	3.933m	9.335ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	1.554m	7.735ms	50	50	100.00
V2	stress_all	hmac_stress_all	38.514m	766.018ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.640s	12.664us	50	50	100.00
V2	intr_test	hmac_intr_test	0.690s	18.679us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	3.640s	1.046ms	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	3.640s	1.046ms	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.730s	79.330us	5	5	100.00
		hmac_csr_rw	0.780s	24.080us	20	20	100.00
		hmac_csr_aliasing	2.640s	136.888us	5	5	100.00
		hmac_same_csr_outstanding	1.350s	502.748us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.730s	79.330us	5	5	100.00
		hmac_csr_rw	0.780s	24.080us	20	20	100.00
		hmac_csr_aliasing	2.640s	136.888us	5	5	100.00
		hmac_same_csr_outstanding	1.350s	502.748us	20	20	100.00
V2		TOTAL			588	590	99.66
V2S	tl_intg_err	hmac_sec_cm	1.000s	354.277us	5	5	100.00
		hmac_tl_intg_err	2.470s	163.668us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	2.470s	163.668us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	4.700s	448.016us	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	1.410h	126.400ms	189	200	94.50
V3		TOTAL			189	200	94.50
		TOTAL			907	920	98.59

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	13	13	12	92.31
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.57	99.53	98.47	100.00	100.00	99.76	99.49	99.72

Failure Buckets

UVM_ERROR (hmac_base_vseq.sv:37) [hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 9 failures:
- Test hmac_stress_all_with_rand_reset has 9 failures.
  - 10.hmac_stress_all_with_rand_reset.32442037353622347265723529228522645823191385513645616120151370978483485177236
    Line 815, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/10.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 109572189243 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 109572189243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 22.hmac_stress_all_with_rand_reset.45153973670519363982058448739049031041220004305348671013661882954908508353807
    Line 1731, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/22.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 232873888270 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 232873888270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test hmac_test_sha_vectors has 2 failures.
  - 3.hmac_test_sha_vectors.11354161662892351648091486279058041686907868860011085953477734357891810892327
    Line 248, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/3.hmac_test_sha_vectors/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 28.hmac_test_sha_vectors.63165166152962670204970112428083560401205547977588199181383250086285037714272
    Line 248, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/28.hmac_test_sha_vectors/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (hmac_base_vseq.sv:37) [hmac_wipe_secret_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 71.hmac_stress_all_with_rand_reset.72854883894126824310957488870383933590485218129104954587255690072085738621998
    Line 421, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/71.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 13213518174 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_wipe_secret_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 13213518174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (hmac_base_vseq.sv:37) [hmac_datapath_stress_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 163.hmac_stress_all_with_rand_reset.76703865488484531695956588048285759279499064630762918437108000987697767907324
    Line 464, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/163.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 94860442951 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_datapath_stress_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 94860442951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

HMAC Simulation Results

Sunday January 14 2024 20:02:50 UTC

GitHub Revision: 5f48fbc0e7

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 17974844803940076144755676589184454804069451770040436570888369542024131598097

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `5f48fbc0e7`