HMAC Simulation Results

Wednesday January 17 2024 20:02:30 UTC

GitHub Revision: `4d88b9516c`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3635458896929517279689574864899235923834879224879080668186365324190153451241

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	4.540s	393.592us	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.770s	27.810us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.790s	42.331us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	9.070s	3.884ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	2.550s	539.205us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	16.143m	122.277ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.790s	42.331us	20	20	100.00
		hmac_csr_aliasing	2.550s	539.205us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	2.031m	9.619ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.117m	4.621ms	50	50	100.00
V2	test_vectors	hmac_test_sha_vectors	8.621m	110.552ms	48	50	96.00
		hmac_test_hmac_vectors	1.240s	203.805us	50	50	100.00
V2	burst_wr	hmac_burst_wr	1.097m	5.845ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	2.619m	11.237ms	50	50	100.00
V2	error	hmac_error	2.971m	14.030ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	1.484m	22.256ms	50	50	100.00
V2	stress_all	hmac_stress_all	34.510m	128.758ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.620s	27.314us	50	50	100.00
V2	intr_test	hmac_intr_test	0.640s	17.357us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	3.780s	69.601us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	3.780s	69.601us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.770s	27.810us	5	5	100.00
		hmac_csr_rw	0.790s	42.331us	20	20	100.00
		hmac_csr_aliasing	2.550s	539.205us	5	5	100.00
		hmac_same_csr_outstanding	1.430s	295.459us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.770s	27.810us	5	5	100.00
		hmac_csr_rw	0.790s	42.331us	20	20	100.00
		hmac_csr_aliasing	2.550s	539.205us	5	5	100.00
		hmac_same_csr_outstanding	1.430s	295.459us	20	20	100.00
V2		TOTAL			588	590	99.66
V2S	tl_intg_err	hmac_sec_cm	1.120s	965.571us	5	5	100.00
		hmac_tl_intg_err	2.630s	686.548us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	2.630s	686.548us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	4.540s	393.592us	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	1.615h	235.895ms	188	200	94.00
V3		TOTAL			188	200	94.00
		TOTAL			906	920	98.48

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	13	13	12	92.31
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.60	99.53	98.58	100.00	100.00	99.76	99.49	99.86

Failure Buckets

UVM_ERROR (hmac_base_vseq.sv:37) [hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 8 failures:
- Test hmac_stress_all_with_rand_reset has 8 failures.
  - 45.hmac_stress_all_with_rand_reset.30193545304962765544682933466853933134342519243910234382006346790461944757531
    Line 984, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/45.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 320138412721 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 320138412721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 73.hmac_stress_all_with_rand_reset.33323690246425203351681971938899889499192160334085718512927851217373055339158
    Line 450, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/73.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 73378339277 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 73378339277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
UVM_ERROR (hmac_base_vseq.sv:37) [hmac_burst_wr_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 2 failures:
- Test hmac_stress_all_with_rand_reset has 2 failures.
  - 0.hmac_stress_all_with_rand_reset.100788421041018536024473385679848632995727385385109591061501087377681381658510
    Line 489, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 33152206577 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_burst_wr_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 33152206577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 193.hmac_stress_all_with_rand_reset.22265080210618624883456805358801324766137839825024750001078908213345853123488
    Line 440, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/193.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 46159975196 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_burst_wr_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 46159975196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test hmac_test_sha_vectors has 2 failures.
  - 18.hmac_test_sha_vectors.97095166633048273337739116144983910716486708460669125492918892481703580215216
    Line 248, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/18.hmac_test_sha_vectors/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 35.hmac_test_sha_vectors.11818251267557866800914458505860319901337116925302904226323240360645722439874
    Line 248, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/35.hmac_test_sha_vectors/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (hmac_base_vseq.sv:37) [hmac_error_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 8.hmac_stress_all_with_rand_reset.98046347647867814780208787616129399678857171304356049648960341749258341677368
    Line 252, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/8.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @   5328287 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @   5328287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (hmac_base_vseq.sv:37) [hmac_back_pressure_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 122.hmac_stress_all_with_rand_reset.92871473703034247484286514808761913544080671344311390362726224785369384133783
    Line 1480, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/122.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 510959370907 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_back_pressure_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 510959370907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

HMAC Simulation Results

Wednesday January 17 2024 20:02:30 UTC

GitHub Revision: 4d88b9516c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3635458896929517279689574864899235923834879224879080668186365324190153451241

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `4d88b9516c`