HMAC Simulation Results

Wednesday January 24 2024 20:02:24 UTC

GitHub Revision: `17d5a97c3b`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 111545506019531132515166311410934274348263845011639206515682989027305484635840

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	4.870s	450.695us	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.740s	97.861us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.750s	22.796us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	8.340s	828.307us	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	2.570s	130.276us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	11.963m	471.123ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.750s	22.796us	20	20	100.00
		hmac_csr_aliasing	2.570s	130.276us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	1.954m	6.380ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.136m	6.571ms	50	50	100.00
V2	test_vectors	hmac_test_sha_vectors	8.595m	79.525ms	43	50	86.00
		hmac_test_hmac_vectors	1.360s	66.388us	50	50	100.00
V2	burst_wr	hmac_burst_wr	1.099m	1.383ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	2.551m	10.791ms	50	50	100.00
V2	error	hmac_error	3.590m	17.543ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	1.622m	33.579ms	50	50	100.00
V2	stress_all	hmac_stress_all	33.461m	659.765ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.660s	22.817us	50	50	100.00
V2	intr_test	hmac_intr_test	0.650s	19.435us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	3.690s	274.621us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	3.690s	274.621us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.740s	97.861us	5	5	100.00
		hmac_csr_rw	0.750s	22.796us	20	20	100.00
		hmac_csr_aliasing	2.570s	130.276us	5	5	100.00
		hmac_same_csr_outstanding	1.400s	309.659us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.740s	97.861us	5	5	100.00
		hmac_csr_rw	0.750s	22.796us	20	20	100.00
		hmac_csr_aliasing	2.570s	130.276us	5	5	100.00
		hmac_same_csr_outstanding	1.400s	309.659us	20	20	100.00
V2		TOTAL			583	590	98.81
V2S	tl_intg_err	hmac_sec_cm	0.970s	1.171ms	5	5	100.00
		hmac_tl_intg_err	2.570s	508.782us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	2.570s	508.782us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	4.870s	450.695us	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	1.678h	113.964ms	184	200	92.00
V3		TOTAL			184	200	92.00
		TOTAL			897	920	97.50

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	13	13	12	92.31
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.60	99.53	98.58	100.00	100.00	99.76	99.49	99.86

Failure Buckets

UVM_ERROR (hmac_base_vseq.sv:37) [hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 10 failures:
- Test hmac_stress_all_with_rand_reset has 10 failures.
  - 26.hmac_stress_all_with_rand_reset.65176937738329503513077494986196862924445443425319474932197928064255361827870
    Line 259, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/26.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 159270140 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 159270140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 34.hmac_stress_all_with_rand_reset.10654399190835165622092786052567241248821161851729090633408532303650049649801
    Line 1182, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/34.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 85085772675 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 85085772675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 7 failures:
- Test hmac_test_sha_vectors has 7 failures.
  - 4.hmac_test_sha_vectors.21452149559938487837984142994481509271870587561530459231306533488482686095969
    Line 248, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/4.hmac_test_sha_vectors/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.hmac_test_sha_vectors.38572074621999848734833462479309213711112071865872866852803740552844208429168
    Line 248, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/5.hmac_test_sha_vectors/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_ERROR (hmac_base_vseq.sv:37) [hmac_back_pressure_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 2 failures:
- Test hmac_stress_all_with_rand_reset has 2 failures.
  - 43.hmac_stress_all_with_rand_reset.58799218514050053210434953816104924831117498155717874952489711111284659113786
    Line 1079, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/43.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 250285544018 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_back_pressure_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 250285544018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 94.hmac_stress_all_with_rand_reset.36129081988759646790567360480253842942169444869559988096076265952187774927642
    Line 1458, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/94.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 92291589461 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_back_pressure_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 92291589461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (hmac_base_vseq.sv:37) [hmac_test_vectors_sha_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 2 failures:
- Test hmac_stress_all_with_rand_reset has 2 failures.
  - 89.hmac_stress_all_with_rand_reset.44870473221097074006422462023951327400185270447391217114627450281235044709037
    Line 402, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/89.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 16411616966 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_test_vectors_sha_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 16411616966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 141.hmac_stress_all_with_rand_reset.103661053063513311050271076523720394125312590953745437132788599361481517369640
    Line 1003, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/141.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 65335957013 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_test_vectors_sha_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 65335957013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (hmac_base_vseq.sv:37) [hmac_smoke_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 49.hmac_stress_all_with_rand_reset.28820032824439251533127633524012343907541045148790302355298468824801599607310
    Line 623, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/49.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 139367325021 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_smoke_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 139367325021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job hmac-sim-vcs_run_default killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *] has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 118.hmac_stress_all_with_rand_reset.70596005162833581952533994830457774866062943459946449036134933983778205273761
    Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/118.hmac_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:4d9ed575-3d93-4328-b6bc-02582287edbb
```

HMAC Simulation Results

Wednesday January 24 2024 20:02:24 UTC

GitHub Revision: 17d5a97c3b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 111545506019531132515166311410934274348263845011639206515682989027305484635840

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `17d5a97c3b`