HMAC Simulation Results

Wednesday January 31 2024 20:02:52 UTC

GitHub Revision: 4ddd81322f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 21932966400645871531253577545734825173576945735198195365995401811578215479543

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 0 50 0.00
V1 csr_hw_reset hmac_csr_hw_reset 0 5 0.00
V1 csr_rw hmac_csr_rw 0 20 0.00
V1 csr_bit_bash hmac_csr_bit_bash 0 5 0.00
V1 csr_aliasing hmac_csr_aliasing 0 5 0.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 0 20 0.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0 20 0.00
hmac_csr_aliasing 0 5 0.00
V1 TOTAL 0 105 0.00
V2 long_msg hmac_long_msg 0 50 0.00
V2 back_pressure hmac_back_pressure 0 50 0.00
V2 test_vectors hmac_test_sha_vectors 0 50 0.00
hmac_test_hmac_vectors 0 50 0.00
V2 burst_wr hmac_burst_wr 0 50 0.00
V2 datapath_stress hmac_datapath_stress 0 50 0.00
V2 error hmac_error 0 50 0.00
V2 wipe_secret hmac_wipe_secret 0 50 0.00
V2 stress_all hmac_stress_all 0 50 0.00
V2 alert_test hmac_alert_test 0 50 0.00
V2 intr_test hmac_intr_test 0 50 0.00
V2 tl_d_oob_addr_access hmac_tl_errors 0 20 0.00
V2 tl_d_illegal_access hmac_tl_errors 0 20 0.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0 5 0.00
hmac_csr_rw 0 20 0.00
hmac_csr_aliasing 0 5 0.00
hmac_same_csr_outstanding 0 20 0.00
V2 tl_d_partial_access hmac_csr_hw_reset 0 5 0.00
hmac_csr_rw 0 20 0.00
hmac_csr_aliasing 0 5 0.00
hmac_same_csr_outstanding 0 20 0.00
V2 TOTAL 0 590 0.00
V2S tl_intg_err hmac_sec_cm 0 5 0.00
hmac_tl_intg_err 0 20 0.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 0 20 0.00
V2S TOTAL 0 25 0.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 0 50 0.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 0 200 0.00
V3 TOTAL 0 200 0.00
TOTAL 0 920 0.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 0 0.00
V2 13 13 0 0.00
V2S 2 2 0 0.00
V3 1 1 0 0.00

Failure Buckets

Past Results