HMAC Simulation Results

Sunday February 04 2024 20:02:57 UTC

GitHub Revision: 0dd29ab736

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 76373007482531906509957308269646114477602578576554530782790132514100107307713

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	4.790s	1.852ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.740s	28.225us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.760s	40.936us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	9.270s	654.035us	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	2.800s	2.132ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	23.239m	306.643ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.760s	40.936us	20	20	100.00
		hmac_csr_aliasing	2.800s	2.132ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	1.741m	33.248ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.104m	3.340ms	50	50	100.00
V2	test_vectors	hmac_test_sha_vectors	8.252m	30.522ms	47	50	94.00
		hmac_test_hmac_vectors	1.260s	179.944us	50	50	100.00
V2	burst_wr	hmac_burst_wr	1.207m	6.931ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	2.598m	2.987ms	50	50	100.00
V2	error	hmac_error	3.806m	19.850ms	49	50	98.00
V2	wipe_secret	hmac_wipe_secret	1.321m	4.355ms	50	50	100.00
V2	stress_all	hmac_stress_all	55.545m	3.102s	50	50	100.00
V2	alert_test	hmac_alert_test	0.640s	13.801us	50	50	100.00
V2	intr_test	hmac_intr_test	0.660s	30.411us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	3.800s	198.554us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	3.800s	198.554us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.740s	28.225us	5	5	100.00
		hmac_csr_rw	0.760s	40.936us	20	20	100.00
		hmac_csr_aliasing	2.800s	2.132ms	5	5	100.00
		hmac_same_csr_outstanding	1.460s	722.164us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.740s	28.225us	5	5	100.00
		hmac_csr_rw	0.760s	40.936us	20	20	100.00
		hmac_csr_aliasing	2.800s	2.132ms	5	5	100.00
		hmac_same_csr_outstanding	1.460s	722.164us	20	20	100.00
V2		TOTAL			586	590	99.32
V2S	tl_intg_err	hmac_sec_cm	0.970s	104.727us	5	5	100.00
		hmac_tl_intg_err	2.520s	1.105ms	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	2.520s	1.105ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	4.790s	1.852ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	1.481h	117.906ms	196	200	98.00
V3		TOTAL			196	200	98.00
		TOTAL			912	920	99.13

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	13	13	11	84.62
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.92	99.55	98.75	100.00	96.30	98.47	99.49	99.86

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:

  • Test hmac_test_sha_vectors has 3 failures.

    • 2.hmac_test_sha_vectors.8189905869002291450273062461476909090371550718896172863064558809165101864070
      Line 248, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_test_sha_vectors/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 9.hmac_test_sha_vectors.115205456668119453386322814739936929411590138663058227554499314820005400920318
      Line 248, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/9.hmac_test_sha_vectors/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

  • Test hmac_error has 1 failures.

    • 47.hmac_error.56741969198541980298992539255192934793370313649334260387864014677797748596181
      Line 271, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/47.hmac_error/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (hmac_base_vseq.sv:37) [hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 3 failures:

  • Test hmac_stress_all_with_rand_reset has 3 failures.

    • 31.hmac_stress_all_with_rand_reset.23691288277282251103022167395504428508886116145641805495449085988321443067562
      Line 488, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/31.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 115933741129 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 115933741129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 45.hmac_stress_all_with_rand_reset.95486466603757509089984132708080444213049323820291490530078214826163178279739
      Line 861, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/45.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 70054180855 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 70054180855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR (hmac_base_vseq.sv:37) [hmac_test_vectors_hmac_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:

  • Test hmac_stress_all_with_rand_reset has 1 failures.

    • 122.hmac_stress_all_with_rand_reset.27616163234135078381638804325018167852138788299219804256579595983538343964825
      Line 2223, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/122.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 218550031109 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_test_vectors_hmac_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 218550031109 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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