HMAC Simulation Results

Wednesday February 07 2024 20:02:46 UTC

GitHub Revision: 5c87d18988

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 42540109002295994234923032062842839138270099951232798724643629525632267455156

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	4.790s	395.197us	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.730s	87.616us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.760s	25.680us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	6.630s	1.832ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	2.000s	106.991us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	13.717m	256.694ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.760s	25.680us	20	20	100.00
		hmac_csr_aliasing	2.000s	106.991us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	1.924m	23.713ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.125m	1.540ms	50	50	100.00
V2	test_vectors	hmac_test_sha_vectors	8.491m	119.155ms	44	50	88.00
		hmac_test_hmac_vectors	1.230s	69.686us	50	50	100.00
V2	burst_wr	hmac_burst_wr	1.250m	10.096ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	2.449m	2.596ms	50	50	100.00
V2	error	hmac_error	3.497m	20.088ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	1.428m	19.087ms	50	50	100.00
V2	stress_all	hmac_stress_all	35.664m	701.396ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.610s	15.119us	50	50	100.00
V2	intr_test	hmac_intr_test	0.700s	14.546us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	3.350s	277.548us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	3.350s	277.548us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.730s	87.616us	5	5	100.00
		hmac_csr_rw	0.760s	25.680us	20	20	100.00
		hmac_csr_aliasing	2.000s	106.991us	5	5	100.00
		hmac_same_csr_outstanding	1.450s	98.492us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.730s	87.616us	5	5	100.00
		hmac_csr_rw	0.760s	25.680us	20	20	100.00
		hmac_csr_aliasing	2.000s	106.991us	5	5	100.00
		hmac_same_csr_outstanding	1.450s	98.492us	20	20	100.00
V2		TOTAL			584	590	98.98
V2S	tl_intg_err	hmac_sec_cm	0.980s	219.482us	5	5	100.00
		hmac_tl_intg_err	2.550s	641.851us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	2.550s	641.851us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	4.790s	395.197us	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	1.804h	382.759ms	191	200	95.50
V3		TOTAL			191	200	95.50
		TOTAL			905	920	98.37

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	13	13	12	92.31
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.45	99.55	98.75	100.00	100.00	98.47	99.49	99.86

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 6 failures:

  • Test hmac_test_sha_vectors has 6 failures.

    • 0.hmac_test_sha_vectors.85486562539624706754389186178906929892358257601934146117830137694112008141145
      Line 248, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_test_sha_vectors/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 17.hmac_test_sha_vectors.14625156959926380572218632663309703445985195177680834630840253998976393283648
      Line 248, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/17.hmac_test_sha_vectors/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 4 more failures.

• UVM_ERROR (hmac_base_vseq.sv:37) [hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 5 failures:

  • Test hmac_stress_all_with_rand_reset has 5 failures.

    • 37.hmac_stress_all_with_rand_reset.26333044177777744101685425260098406158324060824899712169360289823947447194188
      Line 835, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/37.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 73524316616 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 73524316616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 110.hmac_stress_all_with_rand_reset.80013292092905295758895364771649478494213926336406718772949481943424789160011
      Line 323, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/110.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 15846412300 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_stress_all_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 15846412300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 3 more failures.

• UVM_ERROR (hmac_base_vseq.sv:37) [hmac_test_vectors_hmac_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 2 failures:

  • Test hmac_stress_all_with_rand_reset has 2 failures.

    • 103.hmac_stress_all_with_rand_reset.64075639867534437594037487657199741797886653800053821693549351989432747556551
      Line 383, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/103.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 8854536167 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_test_vectors_hmac_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 8854536167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 165.hmac_stress_all_with_rand_reset.29332607761731883811256634899430296530963728255881309511010441960462593931353
      Line 321, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/165.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 17805562952 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_test_vectors_hmac_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 17805562952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (hmac_base_vseq.sv:37) [hmac_wipe_secret_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:

  • Test hmac_stress_all_with_rand_reset has 1 failures.

    • 48.hmac_stress_all_with_rand_reset.27363131793055333060646801010870491071298675741766125877086655071965060203078
      Line 575, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/48.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 14594874201 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_wipe_secret_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 14594874201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (hmac_base_vseq.sv:37) [hmac_burst_wr_vseq] Check failed cfg.hmac_vif.is_idle() == *'b* (* [*] vs * [*]) has 1 failures:

  • Test hmac_stress_all_with_rand_reset has 1 failures.

    • 59.hmac_stress_all_with_rand_reset.6098216188020173027518586352817521873293316785512227401108192979203733597394
      Line 644, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/59.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 36357359986 ps: (hmac_base_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.hmac_burst_wr_vseq] Check failed cfg.hmac_vif.is_idle() == 1'b1 (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 36357359986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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