93b7cb99d8| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | hmac_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | hmac_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | hmac_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | hmac_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | hmac_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | hmac_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | hmac_csr_rw | 0 | 20 | 0.00 | ||
| hmac_csr_aliasing | 0 | 5 | 0.00 | ||||
| V1 | TOTAL | 0 | 105 | 0.00 | |||
| V2 | long_msg | hmac_long_msg | 0 | 50 | 0.00 | ||
| V2 | back_pressure | hmac_back_pressure | 0 | 50 | 0.00 | ||
| V2 | test_vectors | hmac_test_sha_vectors | 0 | 50 | 0.00 | ||
| hmac_test_hmac_vectors | 0 | 50 | 0.00 | ||||
| V2 | burst_wr | hmac_burst_wr | 0 | 50 | 0.00 | ||
| V2 | datapath_stress | hmac_datapath_stress | 0 | 50 | 0.00 | ||
| V2 | error | hmac_error | 0 | 50 | 0.00 | ||
| V2 | wipe_secret | hmac_wipe_secret | 0 | 50 | 0.00 | ||
| V2 | stress_all | hmac_stress_all | 0 | 50 | 0.00 | ||
| V2 | alert_test | hmac_alert_test | 0 | 50 | 0.00 | ||
| V2 | intr_test | hmac_intr_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | hmac_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_illegal_access | hmac_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_outstanding_access | hmac_csr_hw_reset | 0 | 5 | 0.00 | ||
| hmac_csr_rw | 0 | 20 | 0.00 | ||||
| hmac_csr_aliasing | 0 | 5 | 0.00 | ||||
| hmac_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | hmac_csr_hw_reset | 0 | 5 | 0.00 | ||
| hmac_csr_rw | 0 | 20 | 0.00 | ||||
| hmac_csr_aliasing | 0 | 5 | 0.00 | ||||
| hmac_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | TOTAL | 0 | 590 | 0.00 | |||
| V2S | tl_intg_err | hmac_sec_cm | 0 | 5 | 0.00 | ||
| hmac_tl_intg_err | 0 | 20 | 0.00 | ||||
| V2S | sec_cm_bus_integrity | hmac_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | TOTAL | 0 | 25 | 0.00 | |||
| V3 | write_config_and_secret_key_during_msg_wr | hmac_smoke | 0 | 50 | 0.00 | ||
| V3 | stress_all_with_rand_reset | hmac_stress_all_with_rand_reset | 0 | 200 | 0.00 | ||
| V3 | TOTAL | 0 | 200 | 0.00 | |||
| TOTAL | 0 | 920 | 0.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 0 | 0.00 |
| V2 | 13 | 13 | 0 | 0.00 |
| V2S | 2 | 2 | 0 | 0.00 |
| V3 | 1 | 1 | 0 | 0.00 |
Job killed most likely because its dependent job failed. has 922 failures:
0.hmac_smoke.108409664644457610404384717925759736144905294080646399965220517547344075574990
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_smoke/latest/run.log
1.hmac_smoke.10797501509238980800914932124904984256181836978377853003084464826806155753719
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_smoke/latest/run.log
... and 48 more failures.
0.hmac_long_msg.104549337186676139220385442368544124057205812566306077705852883247165531023376
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_long_msg/latest/run.log
1.hmac_long_msg.56931946430069949311966140145382598073943221748115907721007837099735182769062
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_long_msg/latest/run.log
... and 48 more failures.
0.hmac_back_pressure.105336952326326623906389326995305859300677606183270033045146907908139115568052
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_back_pressure/latest/run.log
1.hmac_back_pressure.86296880050828804491016379535785379096111397167049369390043810768027075883861
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_back_pressure/latest/run.log
... and 48 more failures.
0.hmac_datapath_stress.72327789749141175185873409062074594673146289924616811730829357466201211205967
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_datapath_stress/latest/run.log
1.hmac_datapath_stress.57826838550487457732259514751178829488926043993402371210396082788853692684437
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_datapath_stress/latest/run.log
... and 48 more failures.
0.hmac_burst_wr.14081761155384251049784433953408428891378541958585677067118183964122560209919
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_burst_wr/latest/run.log
1.hmac_burst_wr.37091379112958108059348534258285636571555036592935807648379858725579260968469
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_burst_wr/latest/run.log
... and 48 more failures.
Job hmac-sim-vcs_build_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
default
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/default/build.log
Job ID: smart:9ff2d425-1329-4b95-9852-0f7a1c5a0309
Job hmac-sim-vcs_build_cover_reg_top killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
cover_reg_top
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/cover_reg_top/build.log
Job ID: smart:36482e33-5547-476e-8517-bd253000d098