8d1fda3660| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | hmac_smoke | 6.920s | 2.092ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | hmac_csr_hw_reset | 1.150s | 84.336us | 5 | 5 | 100.00 |
| V1 | csr_rw | hmac_csr_rw | 0.980s | 213.787us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | hmac_csr_bit_bash | 15.470s | 1.127ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | hmac_csr_aliasing | 8.910s | 2.300ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | hmac_csr_mem_rw_with_rand_reset | 13.474m | 75.681ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | hmac_csr_rw | 0.980s | 213.787us | 20 | 20 | 100.00 |
| hmac_csr_aliasing | 8.910s | 2.300ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | long_msg | hmac_long_msg | 2.085m | 22.822ms | 50 | 50 | 100.00 |
| V2 | back_pressure | hmac_back_pressure | 1.076m | 1.425ms | 50 | 50 | 100.00 |
| V2 | test_vectors | hmac_test_sha_vectors | 10.328m | 46.346ms | 50 | 50 | 100.00 |
| hmac_test_hmac_vectors | 1.450s | 79.530us | 50 | 50 | 100.00 | ||
| V2 | burst_wr | hmac_burst_wr | 1.271m | 1.609ms | 50 | 50 | 100.00 |
| V2 | datapath_stress | hmac_datapath_stress | 3.021m | 2.821ms | 50 | 50 | 100.00 |
| V2 | error | hmac_error | 4.096m | 26.468ms | 50 | 50 | 100.00 |
| V2 | wipe_secret | hmac_wipe_secret | 1.881m | 7.777ms | 50 | 50 | 100.00 |
| V2 | stress_all | hmac_stress_all | 45.798m | 307.387ms | 50 | 50 | 100.00 |
| V2 | alert_test | hmac_alert_test | 0.630s | 24.388us | 50 | 50 | 100.00 |
| V2 | intr_test | hmac_intr_test | 0.660s | 30.596us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | hmac_tl_errors | 4.180s | 784.106us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | hmac_tl_errors | 4.180s | 784.106us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | hmac_csr_hw_reset | 1.150s | 84.336us | 5 | 5 | 100.00 |
| hmac_csr_rw | 0.980s | 213.787us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 8.910s | 2.300ms | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 2.540s | 160.943us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | hmac_csr_hw_reset | 1.150s | 84.336us | 5 | 5 | 100.00 |
| hmac_csr_rw | 0.980s | 213.787us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 8.910s | 2.300ms | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 2.540s | 160.943us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 590 | 590 | 100.00 | |||
| V2S | tl_intg_err | hmac_sec_cm | 1.300s | 281.655us | 5 | 5 | 100.00 |
| hmac_tl_intg_err | 4.480s | 880.669us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | hmac_tl_intg_err | 4.480s | 880.669us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | write_config_and_secret_key_during_msg_wr | hmac_smoke | 6.920s | 2.092ms | 50 | 50 | 100.00 |
| V3 | stress_all_with_rand_reset | hmac_stress_all_with_rand_reset | 1.831h | 491.137ms | 15 | 200 | 7.50 |
| V3 | TOTAL | 15 | 200 | 7.50 | |||
| TOTAL | 735 | 920 | 79.89 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 13 | 13 | 13 | 100.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 87.04 | 92.80 | 86.09 | 100.00 | 73.68 | 88.15 | 99.49 | 69.08 |
UVM_ERROR (cip_base_vseq.sv:827) [hmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 185 failures:
0.hmac_stress_all_with_rand_reset.25252403484979525590732027307066227823424361899055693416463272778961145033313
Line 34589, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 51153213091 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 51153213091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.hmac_stress_all_with_rand_reset.11650708938055689754961968272482031171552323005256134725267330932414775527232
Line 90048, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 29198452979 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 29198452979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 183 more failures.