bc285b7382| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | hmac_smoke | 7.940s | 612.997us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | hmac_csr_hw_reset | 1.040s | 34.060us | 5 | 5 | 100.00 |
| V1 | csr_rw | hmac_csr_rw | 0.970s | 34.711us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | hmac_csr_bit_bash | 11.320s | 3.730ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | hmac_csr_aliasing | 8.930s | 1.064ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | hmac_csr_mem_rw_with_rand_reset | 12.257m | 158.609ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | hmac_csr_rw | 0.970s | 34.711us | 20 | 20 | 100.00 |
| hmac_csr_aliasing | 8.930s | 1.064ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | long_msg | hmac_long_msg | 2.654m | 107.768ms | 50 | 50 | 100.00 |
| V2 | back_pressure | hmac_back_pressure | 1.299m | 1.602ms | 50 | 50 | 100.00 |
| V2 | test_vectors | hmac_test_sha_vectors | 10.174m | 163.420ms | 50 | 50 | 100.00 |
| hmac_test_hmac_vectors | 1.470s | 75.550us | 50 | 50 | 100.00 | ||
| V2 | burst_wr | hmac_burst_wr | 1.290m | 1.616ms | 50 | 50 | 100.00 |
| V2 | datapath_stress | hmac_datapath_stress | 2.952m | 5.153ms | 50 | 50 | 100.00 |
| V2 | error | hmac_error | 4.282m | 19.373ms | 50 | 50 | 100.00 |
| V2 | wipe_secret | hmac_wipe_secret | 1.940m | 7.042ms | 50 | 50 | 100.00 |
| V2 | stress_all | hmac_stress_all | 42.662m | 132.446ms | 50 | 50 | 100.00 |
| V2 | alert_test | hmac_alert_test | 0.640s | 30.745us | 50 | 50 | 100.00 |
| V2 | intr_test | hmac_intr_test | 0.680s | 86.700us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | hmac_tl_errors | 4.060s | 726.586us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | hmac_tl_errors | 4.060s | 726.586us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | hmac_csr_hw_reset | 1.040s | 34.060us | 5 | 5 | 100.00 |
| hmac_csr_rw | 0.970s | 34.711us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 8.930s | 1.064ms | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 2.600s | 234.249us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | hmac_csr_hw_reset | 1.040s | 34.060us | 5 | 5 | 100.00 |
| hmac_csr_rw | 0.970s | 34.711us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 8.930s | 1.064ms | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 2.600s | 234.249us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 590 | 590 | 100.00 | |||
| V2S | tl_intg_err | hmac_sec_cm | 1.000s | 87.759us | 5 | 5 | 100.00 |
| hmac_tl_intg_err | 4.750s | 233.398us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | hmac_tl_intg_err | 4.750s | 233.398us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | write_config_and_secret_key_during_msg_wr | hmac_smoke | 7.940s | 612.997us | 50 | 50 | 100.00 |
| V3 | stress_all_with_rand_reset | hmac_stress_all_with_rand_reset | 1.880h | 266.164ms | 13 | 200 | 6.50 |
| V3 | TOTAL | 13 | 200 | 6.50 | |||
| TOTAL | 733 | 920 | 79.67 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 13 | 13 | 13 | 100.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 87.39 | 92.80 | 85.92 | 100.00 | 76.32 | 88.15 | 99.49 | 69.08 |
UVM_ERROR (cip_base_vseq.sv:827) [hmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 186 failures:
0.hmac_stress_all_with_rand_reset.75004400730312517360549835899997632506752396692890350247327629000642547920400
Line 9579, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 12329280567 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 12329280567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.hmac_stress_all_with_rand_reset.104025087760279705564661101871738330870201320603404879899757540257794149019840
Line 31536, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 38990785307 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 38990785307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 184 more failures.
UVM_ERROR (cip_base_vseq.sv:753) [hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
96.hmac_stress_all_with_rand_reset.79536360987596633706870049117850781506826556019387814426849715450246577121664
Line 44312, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/96.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 23611843553 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 23611843553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---