e844018f2c| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | hmac_smoke | 7.730s | 650.802us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | hmac_csr_hw_reset | 0.890s | 151.536us | 5 | 5 | 100.00 |
| V1 | csr_rw | hmac_csr_rw | 0.920s | 118.782us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | hmac_csr_bit_bash | 16.050s | 8.109ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | hmac_csr_aliasing | 8.190s | 443.830us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | hmac_csr_mem_rw_with_rand_reset | 10.491m | 647.105ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | hmac_csr_rw | 0.920s | 118.782us | 20 | 20 | 100.00 |
| hmac_csr_aliasing | 8.190s | 443.830us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | long_msg | hmac_long_msg | 2.459m | 11.001ms | 50 | 50 | 100.00 |
| V2 | back_pressure | hmac_back_pressure | 1.137m | 6.857ms | 50 | 50 | 100.00 |
| V2 | test_vectors | hmac_test_sha_vectors | 9.351m | 44.187ms | 50 | 50 | 100.00 |
| hmac_test_hmac_vectors | 1.320s | 252.584us | 50 | 50 | 100.00 | ||
| V2 | burst_wr | hmac_burst_wr | 1.039m | 5.546ms | 50 | 50 | 100.00 |
| V2 | datapath_stress | hmac_datapath_stress | 2.546m | 5.694ms | 50 | 50 | 100.00 |
| V2 | error | hmac_error | 3.598m | 24.273ms | 50 | 50 | 100.00 |
| V2 | wipe_secret | hmac_wipe_secret | 1.554m | 30.407ms | 50 | 50 | 100.00 |
| V2 | stress_all | hmac_stress_all | 42.518m | 776.818ms | 50 | 50 | 100.00 |
| V2 | alert_test | hmac_alert_test | 0.640s | 115.943us | 50 | 50 | 100.00 |
| V2 | intr_test | hmac_intr_test | 0.650s | 18.797us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | hmac_tl_errors | 3.890s | 178.037us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | hmac_tl_errors | 3.890s | 178.037us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | hmac_csr_hw_reset | 0.890s | 151.536us | 5 | 5 | 100.00 |
| hmac_csr_rw | 0.920s | 118.782us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 8.190s | 443.830us | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 2.630s | 935.195us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | hmac_csr_hw_reset | 0.890s | 151.536us | 5 | 5 | 100.00 |
| hmac_csr_rw | 0.920s | 118.782us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 8.190s | 443.830us | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 2.630s | 935.195us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 590 | 590 | 100.00 | |||
| V2S | tl_intg_err | hmac_sec_cm | 0.960s | 90.182us | 5 | 5 | 100.00 |
| hmac_tl_intg_err | 4.170s | 893.749us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | hmac_tl_intg_err | 4.170s | 893.749us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | write_config_and_secret_key_during_msg_wr | hmac_smoke | 7.730s | 650.802us | 50 | 50 | 100.00 |
| V3 | stress_all_with_rand_reset | hmac_stress_all_with_rand_reset | 1.289h | 87.027ms | 21 | 200 | 10.50 |
| V3 | TOTAL | 21 | 200 | 10.50 | |||
| TOTAL | 741 | 920 | 80.54 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 13 | 13 | 13 | 100.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 87.39 | 92.80 | 85.92 | 100.00 | 76.32 | 88.15 | 99.49 | 69.08 |
UVM_ERROR (cip_base_vseq.sv:827) [hmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 178 failures:
0.hmac_stress_all_with_rand_reset.11886576636975131824191648536870498122527385570113406444671148196450701437688
Line 26932, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 12268200142 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 12268200142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.hmac_stress_all_with_rand_reset.14847051414409563174427701310305982559422893473214231618014191385213550693447
Line 57151, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/3.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 5484695260 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 5484695260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 176 more failures.
UVM_ERROR (cip_base_vseq.sv:753) [hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
102.hmac_stress_all_with_rand_reset.107999056558138504066777852253533891175131251761106025051400483498237712009666
Line 323, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/102.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 254162884 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 254162884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---