HMAC Simulation Results

Sunday March 17 2024 19:02:52 UTC

GitHub Revision: c187a82ee8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 28440605375541353837496064678278045899395893237469128852560697715229879921060

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	7.530s	481.156us	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.920s	29.635us	5	5	100.00
V1	csr_rw	hmac_csr_rw	1.040s	105.859us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	15.270s	2.147ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	6.380s	403.729us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	14.997m	88.884ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	1.040s	105.859us	20	20	100.00
		hmac_csr_aliasing	6.380s	403.729us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	2.095m	5.749ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.413m	1.738ms	50	50	100.00
V2	test_vectors	hmac_test_sha_vectors	10.050m	93.502ms	50	50	100.00
		hmac_test_hmac_vectors	1.460s	75.733us	50	50	100.00
V2	burst_wr	hmac_burst_wr	1.293m	3.717ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	3.193m	3.214ms	50	50	100.00
V2	error	hmac_error	3.699m	52.095ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	1.625m	9.714ms	50	50	100.00
V2	stress_all	hmac_stress_all	45.302m	49.021ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.650s	45.781us	50	50	100.00
V2	intr_test	hmac_intr_test	0.670s	62.623us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.090s	327.597us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.090s	327.597us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.920s	29.635us	5	5	100.00
		hmac_csr_rw	1.040s	105.859us	20	20	100.00
		hmac_csr_aliasing	6.380s	403.729us	5	5	100.00
		hmac_same_csr_outstanding	2.570s	186.709us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.920s	29.635us	5	5	100.00
		hmac_csr_rw	1.040s	105.859us	20	20	100.00
		hmac_csr_aliasing	6.380s	403.729us	5	5	100.00
		hmac_same_csr_outstanding	2.570s	186.709us	20	20	100.00
V2		TOTAL			590	590	100.00
V2S	tl_intg_err	hmac_sec_cm	0.950s	56.779us	5	5	100.00
		hmac_tl_intg_err	4.540s	999.173us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.540s	999.173us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	7.530s	481.156us	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	1.167h	299.355ms	14	200	7.00
V3		TOTAL			14	200	7.00
		TOTAL			734	920	79.78

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	13	13	13	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
87.03	92.80	86.04	100.00	73.68	88.15	99.49	69.08

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:827) [hmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 186 failures:
  • Test hmac_stress_all_with_rand_reset has 186 failures.

    • 0.hmac_stress_all_with_rand_reset.86273091729293381156950766115368097626921033959826488115803926692699427450163
      Line 55434, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 167745244871 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 167745244871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.hmac_stress_all_with_rand_reset.99784300110814954035510295995303091705531924615299052291243644480470023754336
      Line 27806, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 17836177365 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 17836177365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 184 more failures.

Past Results

• Latest
• lint
• 2024.03.15_00.06.06
• 2024.03.13_04.02.54
• 2024.03.11_03.16.55
• 2024.03.08_05.07.46
• 2024.03.06_08.08.16
• 2024.03.04_04.53.39