HMAC Simulation Results

Sunday March 24 2024 19:02:40 UTC

GitHub Revision: 70ad420931

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56687816123908180356912499273064417112757374299033127319246303583078997854118

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	7.010s	1.100ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.050s	20.363us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.940s	39.198us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	14.430s	311.054us	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	5.710s	314.866us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	12.210m	519.086ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.940s	39.198us	20	20	100.00
		hmac_csr_aliasing	5.710s	314.866us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	2.260m	17.989ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.157m	3.931ms	50	50	100.00
V2	test_vectors	hmac_test_sha_vectors	9.265m	30.523ms	50	50	100.00
		hmac_test_hmac_vectors	1.430s	82.804us	50	50	100.00
V2	burst_wr	hmac_burst_wr	1.257m	5.482ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	2.774m	11.977ms	50	50	100.00
V2	error	hmac_error	4.118m	37.291ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	1.709m	109.498ms	50	50	100.00
V2	stress_all	hmac_stress_all	32.158m	937.185ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.660s	42.308us	50	50	100.00
V2	intr_test	hmac_intr_test	0.710s	50.857us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.140s	394.582us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.140s	394.582us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.050s	20.363us	5	5	100.00
		hmac_csr_rw	0.940s	39.198us	20	20	100.00
		hmac_csr_aliasing	5.710s	314.866us	5	5	100.00
		hmac_same_csr_outstanding	2.680s	149.605us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.050s	20.363us	5	5	100.00
		hmac_csr_rw	0.940s	39.198us	20	20	100.00
		hmac_csr_aliasing	5.710s	314.866us	5	5	100.00
		hmac_same_csr_outstanding	2.680s	149.605us	20	20	100.00
V2		TOTAL			590	590	100.00
V2S	tl_intg_err	hmac_sec_cm	1.000s	347.496us	5	5	100.00
		hmac_tl_intg_err	4.520s	270.141us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.520s	270.141us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	7.010s	1.100ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	1.025h	363.047ms	10	200	5.00
V3		TOTAL			10	200	5.00
		TOTAL			730	920	79.35

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	13	13	13	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
86.58	92.34	85.35	100.00	73.68	86.11	99.49	69.08

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [hmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 190 failures:
  • Test hmac_stress_all_with_rand_reset has 190 failures.

    • 0.hmac_stress_all_with_rand_reset.66076894509465141369819061977960465305530279811494541357032669913190550876197
      Line 125878, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 65973910169 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 65973910169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.hmac_stress_all_with_rand_reset.38328228981193020585138914370332864234412895061281588279454489324687671280892
      Line 12705, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 8965292429 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 8965292429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 188 more failures.

Past Results

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