HMAC Simulation Results

Tuesday March 19 2024 19:02:40 UTC

GitHub Revision: f7fc348358

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 93166527750821992054916907919379261408154533955814283538537589225972237641118

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	7.080s	398.783us	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.970s	127.211us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.980s	37.769us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	15.840s	3.752ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	9.050s	915.326us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	16.856m	100.376ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.980s	37.769us	20	20	100.00
		hmac_csr_aliasing	9.050s	915.326us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	2.333m	20.078ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.058m	1.687ms	50	50	100.00
V2	test_vectors	hmac_test_sha_vectors	9.470m	181.123ms	50	50	100.00
		hmac_test_hmac_vectors	1.470s	75.200us	50	50	100.00
V2	burst_wr	hmac_burst_wr	1.357m	3.235ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	3.020m	6.251ms	50	50	100.00
V2	error	hmac_error	3.412m	113.472ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	1.846m	15.242ms	50	50	100.00
V2	stress_all	hmac_stress_all	46.661m	61.913ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.640s	89.868us	50	50	100.00
V2	intr_test	hmac_intr_test	0.690s	13.709us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.650s	515.637us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.650s	515.637us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.970s	127.211us	5	5	100.00
		hmac_csr_rw	0.980s	37.769us	20	20	100.00
		hmac_csr_aliasing	9.050s	915.326us	5	5	100.00
		hmac_same_csr_outstanding	2.470s	656.535us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.970s	127.211us	5	5	100.00
		hmac_csr_rw	0.980s	37.769us	20	20	100.00
		hmac_csr_aliasing	9.050s	915.326us	5	5	100.00
		hmac_same_csr_outstanding	2.470s	656.535us	20	20	100.00
V2		TOTAL			590	590	100.00
V2S	tl_intg_err	hmac_sec_cm	1.060s	187.585us	5	5	100.00
		hmac_tl_intg_err	4.490s	859.460us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.490s	859.460us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	7.080s	398.783us	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	55.123m	361.667ms	11	200	5.50
V3		TOTAL			11	200	5.50
		TOTAL			731	920	79.46

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	13	13	13	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
87.03	92.80	85.98	100.00	73.68	88.15	99.49	69.08

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:827) [hmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 189 failures:
  • Test hmac_stress_all_with_rand_reset has 189 failures.

    • 0.hmac_stress_all_with_rand_reset.97996556334158564429378890709052280418422733116054220996427357850032556133042
      Line 4149, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 9824562452 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 9824562452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.hmac_stress_all_with_rand_reset.9125011543319696991112498169667861790742754615927018006586386326533085890022
      Line 95089, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 317193616619 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 317193616619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 187 more failures.

Past Results

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