HMAC Simulation Results

Tuesday March 26 2024 19:03:00 UTC

GitHub Revision: b111fbcef3

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29002153775573720681496722306495080473944791482258036550176866636887326742880

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	7.720s	3.074ms	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	0.980s	133.851us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.980s	108.090us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	16.170s	8.777ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	8.620s	457.276us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	15.932m	388.050ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.980s	108.090us	20	20	100.00
		hmac_csr_aliasing	8.620s	457.276us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	2.421m	28.363ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	1.282m	15.584ms	50	50	100.00
V2	test_vectors	hmac_test_sha_vectors	9.534m	45.433ms	50	50	100.00
		hmac_test_hmac_vectors	1.450s	299.180us	50	50	100.00
V2	burst_wr	hmac_burst_wr	1.242m	7.308ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	2.622m	10.621ms	50	50	100.00
V2	error	hmac_error	4.165m	50.041ms	50	50	100.00
V2	wipe_secret	hmac_wipe_secret	1.655m	11.378ms	50	50	100.00
V2	stress_all	hmac_stress_all	44.144m	94.437ms	50	50	100.00
V2	alert_test	hmac_alert_test	0.640s	23.856us	50	50	100.00
V2	intr_test	hmac_intr_test	0.630s	59.678us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.350s	205.310us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.350s	205.310us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	0.980s	133.851us	5	5	100.00
		hmac_csr_rw	0.980s	108.090us	20	20	100.00
		hmac_csr_aliasing	8.620s	457.276us	5	5	100.00
		hmac_same_csr_outstanding	2.460s	1.438ms	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	0.980s	133.851us	5	5	100.00
		hmac_csr_rw	0.980s	108.090us	20	20	100.00
		hmac_csr_aliasing	8.620s	457.276us	5	5	100.00
		hmac_same_csr_outstanding	2.460s	1.438ms	20	20	100.00
V2		TOTAL			590	590	100.00
V2S	tl_intg_err	hmac_sec_cm	0.950s	374.710us	5	5	100.00
		hmac_tl_intg_err	4.800s	1.033ms	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.800s	1.033ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	7.720s	3.074ms	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	1.232h	125.922ms	9	200	4.50
V3		TOTAL			9	200	4.50
		TOTAL			729	920	79.24

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	13	13	13	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
86.92	92.34	85.07	100.00	76.32	86.11	99.49	69.08

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [hmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 189 failures:
  • Test hmac_stress_all_with_rand_reset has 189 failures.

    • 1.hmac_stress_all_with_rand_reset.113755462855689554434654821850448237584064063277319084587031703894309815320871
      Line 5443, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3266670131 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3266670131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.hmac_stress_all_with_rand_reset.47075829701288474476252338374038519492568765798668250089073286253589303806510
      Line 262820, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/3.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 39029346132 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 39029346132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 187 more failures.

• UVM_ERROR (cip_base_vseq.sv:753) [hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
  • Test hmac_stress_all_with_rand_reset has 2 failures.

    • 2.hmac_stress_all_with_rand_reset.37680144029433920959778401123405723884872502373660180697880045100172088094876
      Line 395, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 111707508 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 111707508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 137.hmac_stress_all_with_rand_reset.69104068781333694525029621390357512016842119968634859895234116840581401927566
      Line 46157, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/137.hmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5321803404 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 5321803404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• 2024.03.25_03.52.33
• 2024.03.22_04.30.43
• 2024.03.20_03.34.25
• 2024.03.18_04.31.46
• 2024.03.15_00.06.06
• 2024.03.13_04.02.54