4ee21f808f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | hmac_smoke | 7.640s | 4.081ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | hmac_csr_hw_reset | 1.030s | 159.117us | 5 | 5 | 100.00 |
| V1 | csr_rw | hmac_csr_rw | 0.960s | 97.185us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | hmac_csr_bit_bash | 14.490s | 4.387ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | hmac_csr_aliasing | 7.620s | 417.492us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | hmac_csr_mem_rw_with_rand_reset | 10.003m | 41.301ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | hmac_csr_rw | 0.960s | 97.185us | 20 | 20 | 100.00 |
| hmac_csr_aliasing | 7.620s | 417.492us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | long_msg | hmac_long_msg | 2.502m | 10.273ms | 50 | 50 | 100.00 |
| V2 | back_pressure | hmac_back_pressure | 1.147m | 1.554ms | 50 | 50 | 100.00 |
| V2 | test_vectors | hmac_test_sha_vectors | 10.721m | 129.786ms | 50 | 50 | 100.00 |
| hmac_test_hmac_vectors | 1.370s | 99.757us | 50 | 50 | 100.00 | ||
| V2 | burst_wr | hmac_burst_wr | 1.126m | 5.179ms | 50 | 50 | 100.00 |
| V2 | datapath_stress | hmac_datapath_stress | 3.239m | 12.403ms | 50 | 50 | 100.00 |
| V2 | error | hmac_error | 3.919m | 24.523ms | 50 | 50 | 100.00 |
| V2 | wipe_secret | hmac_wipe_secret | 1.897m | 20.474ms | 50 | 50 | 100.00 |
| V2 | stress_all | hmac_stress_all | 43.896m | 808.768ms | 50 | 50 | 100.00 |
| V2 | alert_test | hmac_alert_test | 0.640s | 45.072us | 50 | 50 | 100.00 |
| V2 | intr_test | hmac_intr_test | 0.700s | 19.650us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | hmac_tl_errors | 4.010s | 151.919us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | hmac_tl_errors | 4.010s | 151.919us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | hmac_csr_hw_reset | 1.030s | 159.117us | 5 | 5 | 100.00 |
| hmac_csr_rw | 0.960s | 97.185us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 7.620s | 417.492us | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 2.670s | 220.016us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | hmac_csr_hw_reset | 1.030s | 159.117us | 5 | 5 | 100.00 |
| hmac_csr_rw | 0.960s | 97.185us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 7.620s | 417.492us | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 2.670s | 220.016us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 590 | 590 | 100.00 | |||
| V2S | tl_intg_err | hmac_sec_cm | 0.950s | 68.235us | 5 | 5 | 100.00 |
| hmac_tl_intg_err | 4.440s | 290.644us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | hmac_tl_intg_err | 4.440s | 290.644us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | write_config_and_secret_key_during_msg_wr | hmac_smoke | 7.640s | 4.081ms | 50 | 50 | 100.00 |
| V3 | stress_all_with_rand_reset | hmac_stress_all_with_rand_reset | 1.314h | 412.062ms | 18 | 200 | 9.00 |
| V3 | TOTAL | 18 | 200 | 9.00 | |||
| TOTAL | 738 | 920 | 80.22 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 13 | 13 | 13 | 100.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 86.92 | 92.34 | 85.07 | 100.00 | 76.32 | 86.11 | 99.49 | 69.08 |
UVM_ERROR (cip_base_vseq.sv:829) [hmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 179 failures:
0.hmac_stress_all_with_rand_reset.88315838131398515181518109391203055848447432447601868137118232310852714711810
Line 37751, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4255247755 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4255247755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.hmac_stress_all_with_rand_reset.39451350362882541140619780403087850988960034493314563586772346823999885664114
Line 6921, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 25997919345 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 25997919345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 177 more failures.
UVM_ERROR (cip_base_vseq.sv:753) [hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 3 failures:
70.hmac_stress_all_with_rand_reset.69943681396566557998372383096693112353632917213766756141528274297395068322963
Line 739, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/70.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 277100374 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 277100374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
109.hmac_stress_all_with_rand_reset.23033122937116292509407482189980126581934211192836698491545862514555395570374
Line 421701, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/109.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 87833412313 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 87833412313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.