HMAC Simulation Results

Sunday March 31 2024 19:03:23 UTC

GitHub Revision: 919341eb22

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 80856351313811177568455658403012118288310064949310327557570531903004064389549

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 7.320s 488.424us 50 50 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.990s 613.392us 5 5 100.00
V1 csr_rw hmac_csr_rw 0.930s 143.823us 20 20 100.00
V1 csr_bit_bash hmac_csr_bit_bash 15.790s 4.222ms 5 5 100.00
V1 csr_aliasing hmac_csr_aliasing 8.100s 610.013us 5 5 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 10.973m 240.626ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.930s 143.823us 20 20 100.00
hmac_csr_aliasing 8.100s 610.013us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 long_msg hmac_long_msg 2.331m 6.902ms 50 50 100.00
V2 back_pressure hmac_back_pressure 1.086m 3.282ms 50 50 100.00
V2 test_vectors hmac_test_sha_vectors 9.671m 32.364ms 50 50 100.00
hmac_test_hmac_vectors 1.440s 300.142us 50 50 100.00
V2 burst_wr hmac_burst_wr 1.178m 2.820ms 50 50 100.00
V2 datapath_stress hmac_datapath_stress 3.232m 60.349ms 50 50 100.00
V2 error hmac_error 4.093m 17.287ms 50 50 100.00
V2 wipe_secret hmac_wipe_secret 1.640m 4.907ms 50 50 100.00
V2 save_and_restore save_and_restore 0 0 --
V2 fifo_empty_status_interrupt fifo_empty_status_interrupt 0 0 --
V2 wide_digest_configurable_key_length wide_digest_configurable_key_length 0 0 --
V2 stress_all hmac_stress_all 36.762m 51.864ms 50 50 100.00
V2 alert_test hmac_alert_test 0.630s 53.859us 50 50 100.00
V2 intr_test hmac_intr_test 0.680s 17.521us 50 50 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 4.500s 1.006ms 20 20 100.00
V2 tl_d_illegal_access hmac_tl_errors 4.500s 1.006ms 20 20 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.990s 613.392us 5 5 100.00
hmac_csr_rw 0.930s 143.823us 20 20 100.00
hmac_csr_aliasing 8.100s 610.013us 5 5 100.00
hmac_same_csr_outstanding 2.390s 120.029us 20 20 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.990s 613.392us 5 5 100.00
hmac_csr_rw 0.930s 143.823us 20 20 100.00
hmac_csr_aliasing 8.100s 610.013us 5 5 100.00
hmac_same_csr_outstanding 2.390s 120.029us 20 20 100.00
V2 TOTAL 590 590 100.00
V2S tl_intg_err hmac_sec_cm 1.030s 95.592us 5 5 100.00
hmac_tl_intg_err 4.310s 447.816us 20 20 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 4.310s 447.816us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 7.320s 488.424us 50 50 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.603h 572.423ms 11 200 5.50
V3 TOTAL 11 200 5.50
TOTAL 731 920 79.46

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 16 13 13 81.25
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
86.55 92.46 85.17 100.00 73.68 85.93 99.49 69.08

Failure Buckets

Past Results