1fbe1ece8d| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | hmac_smoke | 6.990s | 576.004us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | hmac_csr_hw_reset | 1.050s | 44.636us | 5 | 5 | 100.00 |
| V1 | csr_rw | hmac_csr_rw | 1.000s | 18.224us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | hmac_csr_bit_bash | 10.800s | 11.764ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | hmac_csr_aliasing | 8.300s | 606.269us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | hmac_csr_mem_rw_with_rand_reset | 13.260m | 83.221ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | hmac_csr_rw | 1.000s | 18.224us | 20 | 20 | 100.00 |
| hmac_csr_aliasing | 8.300s | 606.269us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | long_msg | hmac_long_msg | 2.505m | 10.567ms | 50 | 50 | 100.00 |
| V2 | back_pressure | hmac_back_pressure | 1.136m | 1.597ms | 50 | 50 | 100.00 |
| V2 | test_vectors | hmac_test_sha_vectors | 9.459m | 44.570ms | 50 | 50 | 100.00 |
| hmac_test_hmac_vectors | 1.430s | 280.477us | 50 | 50 | 100.00 | ||
| V2 | burst_wr | hmac_burst_wr | 1.480m | 21.805ms | 50 | 50 | 100.00 |
| V2 | datapath_stress | hmac_datapath_stress | 2.849m | 10.747ms | 50 | 50 | 100.00 |
| V2 | error | hmac_error | 4.328m | 171.295ms | 50 | 50 | 100.00 |
| V2 | wipe_secret | hmac_wipe_secret | 1.912m | 29.939ms | 50 | 50 | 100.00 |
| V2 | save_and_restore | save_and_restore | 0 | 0 | -- | ||
| V2 | fifo_empty_status_interrupt | fifo_empty_status_interrupt | 0 | 0 | -- | ||
| V2 | wide_digest_configurable_key_length | wide_digest_configurable_key_length | 0 | 0 | -- | ||
| V2 | stress_all | hmac_stress_all | 45.669m | 198.529ms | 50 | 50 | 100.00 |
| V2 | alert_test | hmac_alert_test | 0.640s | 20.827us | 50 | 50 | 100.00 |
| V2 | intr_test | hmac_intr_test | 0.700s | 49.150us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | hmac_tl_errors | 3.870s | 2.271ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | hmac_tl_errors | 3.870s | 2.271ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | hmac_csr_hw_reset | 1.050s | 44.636us | 5 | 5 | 100.00 |
| hmac_csr_rw | 1.000s | 18.224us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 8.300s | 606.269us | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 2.600s | 1.502ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | hmac_csr_hw_reset | 1.050s | 44.636us | 5 | 5 | 100.00 |
| hmac_csr_rw | 1.000s | 18.224us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 8.300s | 606.269us | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 2.600s | 1.502ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 590 | 590 | 100.00 | |||
| V2S | tl_intg_err | hmac_sec_cm | 1.010s | 161.153us | 5 | 5 | 100.00 |
| hmac_tl_intg_err | 4.260s | 865.032us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | hmac_tl_intg_err | 4.260s | 865.032us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | write_config_and_secret_key_during_msg_wr | hmac_smoke | 6.990s | 576.004us | 50 | 50 | 100.00 |
| V3 | stress_all_with_rand_reset | hmac_stress_all_with_rand_reset | 1.028h | 288.611ms | 11 | 200 | 5.50 |
| V3 | TOTAL | 11 | 200 | 5.50 | |||
| TOTAL | 731 | 920 | 79.46 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 16 | 13 | 13 | 81.25 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 86.58 | 92.46 | 85.39 | 100.00 | 73.68 | 85.93 | 99.49 | 69.08 |
UVM_ERROR (cip_base_vseq.sv:829) [hmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 188 failures:
0.hmac_stress_all_with_rand_reset.35747982351024212173306847448037181796888689406127121596491291367077789269412
Line 5929, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7694776063 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 7694776063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.hmac_stress_all_with_rand_reset.115179728066733037782782371071997098717698228061116539962484008251554176914828
Line 17718, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 38500110465 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 38500110465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 186 more failures.
UVM_ERROR (hmac_scoreboard.sv:289) [scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (* [*] vs * [*]) has 1 failures:
128.hmac_stress_all_with_rand_reset.69018789073093095284956178026185703284709354810361029874146895276961315540675
Line 179146, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/128.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 18627485016 ps: (hmac_scoreboard.sv:289) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (0 [0x0] vs 3150674949 [0xbbcb7c05])
UVM_INFO @ 18627485016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---