7773b039d0| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | hmac_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | hmac_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | hmac_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | hmac_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | hmac_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | hmac_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | hmac_csr_rw | 0 | 20 | 0.00 | ||
| hmac_csr_aliasing | 0 | 5 | 0.00 | ||||
| V1 | TOTAL | 0 | 105 | 0.00 | |||
| V2 | long_msg | hmac_long_msg | 0 | 50 | 0.00 | ||
| V2 | back_pressure | hmac_back_pressure | 0 | 50 | 0.00 | ||
| V2 | test_vectors | hmac_test_sha_vectors | 0 | 50 | 0.00 | ||
| hmac_test_hmac_vectors | 0 | 50 | 0.00 | ||||
| V2 | burst_wr | hmac_burst_wr | 0 | 50 | 0.00 | ||
| V2 | datapath_stress | hmac_datapath_stress | 0 | 50 | 0.00 | ||
| V2 | error | hmac_error | 0 | 50 | 0.00 | ||
| V2 | wipe_secret | hmac_wipe_secret | 0 | 50 | 0.00 | ||
| V2 | save_and_restore | save_and_restore | 0 | 0 | -- | ||
| V2 | fifo_empty_status_interrupt | fifo_empty_status_interrupt | 0 | 0 | -- | ||
| V2 | wide_digest_configurable_key_length | wide_digest_configurable_key_length | 0 | 0 | -- | ||
| V2 | stress_all | hmac_stress_all | 0 | 50 | 0.00 | ||
| V2 | alert_test | hmac_alert_test | 0 | 50 | 0.00 | ||
| V2 | intr_test | hmac_intr_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | hmac_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_illegal_access | hmac_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_outstanding_access | hmac_csr_hw_reset | 0 | 5 | 0.00 | ||
| hmac_csr_rw | 0 | 20 | 0.00 | ||||
| hmac_csr_aliasing | 0 | 5 | 0.00 | ||||
| hmac_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | hmac_csr_hw_reset | 0 | 5 | 0.00 | ||
| hmac_csr_rw | 0 | 20 | 0.00 | ||||
| hmac_csr_aliasing | 0 | 5 | 0.00 | ||||
| hmac_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | TOTAL | 0 | 590 | 0.00 | |||
| V2S | tl_intg_err | hmac_sec_cm | 0 | 5 | 0.00 | ||
| hmac_tl_intg_err | 0 | 20 | 0.00 | ||||
| V2S | sec_cm_bus_integrity | hmac_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | TOTAL | 0 | 25 | 0.00 | |||
| V3 | write_config_and_secret_key_during_msg_wr | hmac_smoke | 0 | 50 | 0.00 | ||
| V3 | stress_all_with_rand_reset | hmac_stress_all_with_rand_reset | 0 | 200 | 0.00 | ||
| V3 | TOTAL | 0 | 200 | 0.00 | |||
| TOTAL | 0 | 920 | 0.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 0 | 0.00 |
| V2 | 16 | 13 | 0 | 0.00 |
| V2S | 2 | 2 | 0 | 0.00 |
| V3 | 1 | 1 | 0 | 0.00 |
User terminated with CTRL-C has 920 failures:
0.hmac_smoke.70021803720861029101935331273398184239198363269591764686824687576880340543636
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_smoke/latest/run.log
1.hmac_smoke.105567365118796031776121249363239079280613808998193683443303553857922278439939
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_smoke/latest/run.log
... and 48 more failures.
0.hmac_long_msg.89969666593753030659328954517075434144393832555978119463169281032947486127710
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_long_msg/latest/run.log
1.hmac_long_msg.29262523978767634131320101435493110951626203646207788084691658119505306916670
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_long_msg/latest/run.log
... and 48 more failures.
0.hmac_back_pressure.63019671907664508623019769894374562450805287698352766434349797810062055366792
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_back_pressure/latest/run.log
1.hmac_back_pressure.64178752806593531582930814800198689922516008291719699622988817896959944416580
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_back_pressure/latest/run.log
... and 48 more failures.
0.hmac_datapath_stress.34178554751982940554059430261917512682600401998929121333553447190364693870884
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_datapath_stress/latest/run.log
1.hmac_datapath_stress.90197104642118114219870936728904356644926836263419386061850603042227137223953
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_datapath_stress/latest/run.log
... and 48 more failures.
0.hmac_burst_wr.33542416539501035076158015827764996448367728565479706845204351030188877691710
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_burst_wr/latest/run.log
1.hmac_burst_wr.115214481236633135090614999884719229539250387757449700246947710411661754196658
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_burst_wr/latest/run.log
... and 48 more failures.
Job killed most likely because its dependent job failed. has 2 failures:
cov_merge
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/cov_merge/merged.vdb/cov_merge.log
cov_report
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/cov_report/cov_report.log