1f410ef5dc| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | hmac_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | hmac_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | hmac_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | hmac_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | hmac_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | hmac_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | hmac_csr_rw | 0 | 20 | 0.00 | ||
| hmac_csr_aliasing | 0 | 5 | 0.00 | ||||
| V1 | TOTAL | 0 | 105 | 0.00 | |||
| V2 | long_msg | hmac_long_msg | 0 | 50 | 0.00 | ||
| V2 | back_pressure | hmac_back_pressure | 0 | 50 | 0.00 | ||
| V2 | test_vectors | hmac_test_sha_vectors | 0 | 50 | 0.00 | ||
| hmac_test_hmac_vectors | 0 | 50 | 0.00 | ||||
| V2 | burst_wr | hmac_burst_wr | 0 | 50 | 0.00 | ||
| V2 | datapath_stress | hmac_datapath_stress | 0 | 50 | 0.00 | ||
| V2 | error | hmac_error | 0 | 50 | 0.00 | ||
| V2 | wipe_secret | hmac_wipe_secret | 0 | 50 | 0.00 | ||
| V2 | save_and_restore | save_and_restore | 0 | 0 | -- | ||
| V2 | fifo_empty_status_interrupt | fifo_empty_status_interrupt | 0 | 0 | -- | ||
| V2 | wide_digest_configurable_key_length | wide_digest_configurable_key_length | 0 | 0 | -- | ||
| V2 | stress_all | hmac_stress_all | 0 | 50 | 0.00 | ||
| V2 | alert_test | hmac_alert_test | 0 | 50 | 0.00 | ||
| V2 | intr_test | hmac_intr_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | hmac_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_illegal_access | hmac_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_outstanding_access | hmac_csr_hw_reset | 0 | 5 | 0.00 | ||
| hmac_csr_rw | 0 | 20 | 0.00 | ||||
| hmac_csr_aliasing | 0 | 5 | 0.00 | ||||
| hmac_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | hmac_csr_hw_reset | 0 | 5 | 0.00 | ||
| hmac_csr_rw | 0 | 20 | 0.00 | ||||
| hmac_csr_aliasing | 0 | 5 | 0.00 | ||||
| hmac_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | TOTAL | 0 | 590 | 0.00 | |||
| V2S | tl_intg_err | hmac_sec_cm | 0 | 5 | 0.00 | ||
| hmac_tl_intg_err | 0 | 20 | 0.00 | ||||
| V2S | sec_cm_bus_integrity | hmac_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | TOTAL | 0 | 25 | 0.00 | |||
| V3 | write_config_and_secret_key_during_msg_wr | hmac_smoke | 0 | 50 | 0.00 | ||
| V3 | stress_all_with_rand_reset | hmac_stress_all_with_rand_reset | 0 | 200 | 0.00 | ||
| V3 | TOTAL | 0 | 200 | 0.00 | |||
| TOTAL | 0 | 920 | 0.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 0 | 0.00 |
| V2 | 16 | 13 | 0 | 0.00 |
| V2S | 2 | 2 | 0 | 0.00 |
| V3 | 1 | 1 | 0 | 0.00 |
User terminated with CTRL-C has 920 failures:
0.hmac_smoke.102101501548282435943832736951734898053613630720883061783762828934667202801903
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_smoke/latest/run.log
1.hmac_smoke.20678618194376023997935115457590986494560968717587035012055862787044902506050
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_smoke/latest/run.log
... and 48 more failures.
0.hmac_long_msg.17358430828234210169424220781163082167249768365498886937095770185278107489411
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_long_msg/latest/run.log
1.hmac_long_msg.44166819199414420291549109030063071127778206325329466489862746271892332098365
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_long_msg/latest/run.log
... and 48 more failures.
0.hmac_back_pressure.94857151090679844553843663896809874496375549559799605118354505873328795773253
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_back_pressure/latest/run.log
1.hmac_back_pressure.6432485079276070333217246257401467392277495037724765783221398035271250607308
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_back_pressure/latest/run.log
... and 48 more failures.
0.hmac_datapath_stress.59694816323540422398546226660420334097223848664220931207867279764728546649826
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_datapath_stress/latest/run.log
1.hmac_datapath_stress.41477276514602092193039316574494485357712491044688013031358266017358311389875
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_datapath_stress/latest/run.log
... and 48 more failures.
0.hmac_burst_wr.51253317648810749620652188924279222094336367428199003981647831990494605986619
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_burst_wr/latest/run.log
1.hmac_burst_wr.35574263829020917808195431647482222439461696995162568029849820763285417420510
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_burst_wr/latest/run.log
... and 48 more failures.
Job killed most likely because its dependent job failed. has 2 failures:
cov_merge
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/cov_merge/merged.vdb/cov_merge.log
cov_report
Log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/cov_report/cov_report.log