9f4903e77a| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | hmac_smoke | 6.880s | 1.826ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | hmac_csr_hw_reset | 0.960s | 261.516us | 5 | 5 | 100.00 |
| V1 | csr_rw | hmac_csr_rw | 0.970s | 40.088us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | hmac_csr_bit_bash | 14.630s | 632.342us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | hmac_csr_aliasing | 8.570s | 2.293ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | hmac_csr_mem_rw_with_rand_reset | 12.891m | 358.623ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | hmac_csr_rw | 0.970s | 40.088us | 20 | 20 | 100.00 |
| hmac_csr_aliasing | 8.570s | 2.293ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | long_msg | hmac_long_msg | 2.126m | 20.408ms | 50 | 50 | 100.00 |
| V2 | back_pressure | hmac_back_pressure | 1.252m | 6.910ms | 50 | 50 | 100.00 |
| V2 | test_vectors | hmac_test_sha_vectors | 9.455m | 116.938ms | 50 | 50 | 100.00 |
| hmac_test_hmac_vectors | 1.390s | 198.298us | 50 | 50 | 100.00 | ||
| V2 | burst_wr | hmac_burst_wr | 1.075m | 17.235ms | 50 | 50 | 100.00 |
| V2 | datapath_stress | hmac_datapath_stress | 2.765m | 56.438ms | 50 | 50 | 100.00 |
| V2 | error | hmac_error | 4.600m | 35.101ms | 50 | 50 | 100.00 |
| V2 | wipe_secret | hmac_wipe_secret | 1.535m | 9.821ms | 50 | 50 | 100.00 |
| V2 | save_and_restore | save_and_restore | 0 | 0 | -- | ||
| V2 | fifo_empty_status_interrupt | fifo_empty_status_interrupt | 0 | 0 | -- | ||
| V2 | wide_digest_configurable_key_length | wide_digest_configurable_key_length | 0 | 0 | -- | ||
| V2 | stress_all | hmac_stress_all | 59.311m | 409.482ms | 50 | 50 | 100.00 |
| V2 | alert_test | hmac_alert_test | 0.630s | 13.568us | 50 | 50 | 100.00 |
| V2 | intr_test | hmac_intr_test | 0.670s | 17.085us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | hmac_tl_errors | 4.060s | 1.070ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | hmac_tl_errors | 4.060s | 1.070ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | hmac_csr_hw_reset | 0.960s | 261.516us | 5 | 5 | 100.00 |
| hmac_csr_rw | 0.970s | 40.088us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 8.570s | 2.293ms | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 2.550s | 161.450us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | hmac_csr_hw_reset | 0.960s | 261.516us | 5 | 5 | 100.00 |
| hmac_csr_rw | 0.970s | 40.088us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 8.570s | 2.293ms | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 2.550s | 161.450us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 590 | 590 | 100.00 | |||
| V2S | tl_intg_err | hmac_sec_cm | 1.100s | 612.137us | 5 | 5 | 100.00 |
| hmac_tl_intg_err | 4.450s | 242.660us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | hmac_tl_intg_err | 4.450s | 242.660us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | write_config_and_secret_key_during_msg_wr | hmac_smoke | 6.880s | 1.826ms | 50 | 50 | 100.00 |
| V3 | stress_all_with_rand_reset | hmac_stress_all_with_rand_reset | 1.951h | 536.949ms | 13 | 200 | 6.50 |
| V3 | TOTAL | 13 | 200 | 6.50 | |||
| TOTAL | 733 | 920 | 79.67 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 16 | 13 | 13 | 81.25 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 86.55 | 92.46 | 85.17 | 100.00 | 73.68 | 85.93 | 99.49 | 69.08 |
UVM_ERROR (cip_base_vseq.sv:829) [hmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 186 failures:
0.hmac_stress_all_with_rand_reset.81167983437199552133254150312713500244763453130853014025242719578948751043080
Line 491280, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 74309643871 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 74309643871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.hmac_stress_all_with_rand_reset.25610694080482940490952241607387924112567185958543985131708369412396312117852
Line 52314, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 63778830751 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 63778830751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 184 more failures.
UVM_ERROR (cip_base_vseq.sv:753) [hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
188.hmac_stress_all_with_rand_reset.9624270514926824815164809095183284605597470661930750830495568228952473315571
Line 520, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/188.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 30750401 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 30750401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---