1c75f24e99| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | hmac_smoke | 7.260s | 1.226ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | hmac_csr_hw_reset | 1.020s | 39.327us | 5 | 5 | 100.00 |
| V1 | csr_rw | hmac_csr_rw | 0.980s | 28.623us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | hmac_csr_bit_bash | 17.770s | 4.382ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | hmac_csr_aliasing | 8.090s | 163.284us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | hmac_csr_mem_rw_with_rand_reset | 6.454m | 25.249ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | hmac_csr_rw | 0.980s | 28.623us | 20 | 20 | 100.00 |
| hmac_csr_aliasing | 8.090s | 163.284us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | long_msg | hmac_long_msg | 2.148m | 49.498ms | 50 | 50 | 100.00 |
| V2 | back_pressure | hmac_back_pressure | 1.290m | 6.963ms | 50 | 50 | 100.00 |
| V2 | test_vectors | hmac_test_sha_vectors | 9.656m | 115.676ms | 50 | 50 | 100.00 |
| hmac_test_hmac_vectors | 1.380s | 145.925us | 50 | 50 | 100.00 | ||
| V2 | burst_wr | hmac_burst_wr | 1.169m | 2.255ms | 50 | 50 | 100.00 |
| V2 | datapath_stress | hmac_datapath_stress | 2.912m | 2.830ms | 50 | 50 | 100.00 |
| V2 | error | hmac_error | 4.676m | 40.749ms | 50 | 50 | 100.00 |
| V2 | wipe_secret | hmac_wipe_secret | 1.715m | 10.452ms | 50 | 50 | 100.00 |
| V2 | save_and_restore | save_and_restore | 0 | 0 | -- | ||
| V2 | fifo_empty_status_interrupt | fifo_empty_status_interrupt | 0 | 0 | -- | ||
| V2 | wide_digest_configurable_key_length | wide_digest_configurable_key_length | 0 | 0 | -- | ||
| V2 | stress_all | hmac_stress_all | 41.290m | 594.306ms | 50 | 50 | 100.00 |
| V2 | alert_test | hmac_alert_test | 0.660s | 28.728us | 50 | 50 | 100.00 |
| V2 | intr_test | hmac_intr_test | 0.680s | 140.281us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | hmac_tl_errors | 4.760s | 232.364us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | hmac_tl_errors | 4.760s | 232.364us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | hmac_csr_hw_reset | 1.020s | 39.327us | 5 | 5 | 100.00 |
| hmac_csr_rw | 0.980s | 28.623us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 8.090s | 163.284us | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 2.670s | 938.801us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | hmac_csr_hw_reset | 1.020s | 39.327us | 5 | 5 | 100.00 |
| hmac_csr_rw | 0.980s | 28.623us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 8.090s | 163.284us | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 2.670s | 938.801us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 590 | 590 | 100.00 | |||
| V2S | tl_intg_err | hmac_sec_cm | 0.970s | 107.374us | 5 | 5 | 100.00 |
| hmac_tl_intg_err | 4.590s | 1.096ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | hmac_tl_intg_err | 4.590s | 1.096ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | write_config_and_secret_key_during_msg_wr | hmac_smoke | 7.260s | 1.226ms | 50 | 50 | 100.00 |
| V3 | stress_all_with_rand_reset | hmac_stress_all_with_rand_reset | 54.527m | 60.309ms | 14 | 200 | 7.00 |
| V3 | TOTAL | 14 | 200 | 7.00 | |||
| TOTAL | 734 | 920 | 79.78 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 16 | 13 | 13 | 81.25 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 86.55 | 92.46 | 85.19 | 100.00 | 73.68 | 85.93 | 99.49 | 69.08 |
UVM_ERROR (cip_base_vseq.sv:829) [hmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 186 failures:
0.hmac_stress_all_with_rand_reset.87660397163629209945892426358319725978396614430755900842984850957641208774868
Line 8705, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 10493477504 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 10493477504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.hmac_stress_all_with_rand_reset.25763152435346552630186140410166201252607057793606456657351782162169842147306
Line 21724, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 27970433356 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 27970433356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 184 more failures.