d3942ca074| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | hmac_smoke | 7.300s | 2.817ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | hmac_csr_hw_reset | 1.010s | 40.062us | 5 | 5 | 100.00 |
| V1 | csr_rw | hmac_csr_rw | 1.030s | 29.278us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | hmac_csr_bit_bash | 16.950s | 6.245ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | hmac_csr_aliasing | 3.610s | 393.581us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | hmac_csr_mem_rw_with_rand_reset | 15.869m | 64.270ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | hmac_csr_rw | 1.030s | 29.278us | 20 | 20 | 100.00 |
| hmac_csr_aliasing | 3.610s | 393.581us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | long_msg | hmac_long_msg | 1.949m | 6.371ms | 50 | 50 | 100.00 |
| V2 | back_pressure | hmac_back_pressure | 1.132m | 1.882ms | 50 | 50 | 100.00 |
| V2 | test_vectors | hmac_test_sha_vectors | 9.187m | 181.405ms | 50 | 50 | 100.00 |
| hmac_test_hmac_vectors | 1.340s | 331.403us | 50 | 50 | 100.00 | ||
| V2 | burst_wr | hmac_burst_wr | 1.269m | 1.551ms | 50 | 50 | 100.00 |
| V2 | datapath_stress | hmac_datapath_stress | 2.796m | 2.996ms | 50 | 50 | 100.00 |
| V2 | error | hmac_error | 3.598m | 17.291ms | 50 | 50 | 100.00 |
| V2 | wipe_secret | hmac_wipe_secret | 1.748m | 5.157ms | 50 | 50 | 100.00 |
| V2 | save_and_restore | save_and_restore | 0 | 0 | -- | ||
| V2 | fifo_empty_status_interrupt | fifo_empty_status_interrupt | 0 | 0 | -- | ||
| V2 | wide_digest_configurable_key_length | wide_digest_configurable_key_length | 0 | 0 | -- | ||
| V2 | stress_all | hmac_stress_all | 50.443m | 229.613ms | 50 | 50 | 100.00 |
| V2 | alert_test | hmac_alert_test | 0.630s | 15.777us | 50 | 50 | 100.00 |
| V2 | intr_test | hmac_intr_test | 0.670s | 18.913us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | hmac_tl_errors | 5.350s | 770.043us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | hmac_tl_errors | 5.350s | 770.043us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | hmac_csr_hw_reset | 1.010s | 40.062us | 5 | 5 | 100.00 |
| hmac_csr_rw | 1.030s | 29.278us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 3.610s | 393.581us | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 2.580s | 150.751us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | hmac_csr_hw_reset | 1.010s | 40.062us | 5 | 5 | 100.00 |
| hmac_csr_rw | 1.030s | 29.278us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 3.610s | 393.581us | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 2.580s | 150.751us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 590 | 590 | 100.00 | |||
| V2S | tl_intg_err | hmac_sec_cm | 1.000s | 1.951ms | 5 | 5 | 100.00 |
| hmac_tl_intg_err | 4.870s | 1.926ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | hmac_tl_intg_err | 4.870s | 1.926ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | write_config_and_secret_key_during_msg_wr | hmac_smoke | 7.300s | 2.817ms | 50 | 50 | 100.00 |
| V3 | stress_all_with_rand_reset | hmac_stress_all_with_rand_reset | 1.556h | 105.288ms | 7 | 200 | 3.50 |
| V3 | TOTAL | 7 | 200 | 3.50 | |||
| TOTAL | 727 | 920 | 79.02 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 16 | 13 | 13 | 81.25 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 86.93 | 92.46 | 85.24 | 100.00 | 76.32 | 85.93 | 99.49 | 69.08 |
UVM_ERROR (cip_base_vseq.sv:829) [hmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 190 failures:
0.hmac_stress_all_with_rand_reset.55142724721805184156246448262992788336249566544098260027321996699395795355273
Line 76796, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 30400424510 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 30400424510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.hmac_stress_all_with_rand_reset.26298589885712393305127696109793576471239801355061687199549728351041716770785
Line 41391, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 9968865241 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 9968865241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 188 more failures.
UVM_ERROR (cip_base_vseq.sv:753) [hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 3 failures:
54.hmac_stress_all_with_rand_reset.102976483459731431395799440293878099429109204472657913055339279384618987036344
Line 109430, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/54.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 40120908146 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 40120908146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
100.hmac_stress_all_with_rand_reset.17720652721807806360506656779386580236025384764491653624028789860862424895303
Line 25363, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/100.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3304479139 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 3304479139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.