4fd94db59a| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | hmac_smoke | 7.060s | 6.312ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | hmac_csr_hw_reset | 1.000s | 35.139us | 5 | 5 | 100.00 |
| V1 | csr_rw | hmac_csr_rw | 0.970s | 380.948us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | hmac_csr_bit_bash | 17.050s | 6.257ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | hmac_csr_aliasing | 8.670s | 2.632ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | hmac_csr_mem_rw_with_rand_reset | 6.616m | 153.065ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | hmac_csr_rw | 0.970s | 380.948us | 20 | 20 | 100.00 |
| hmac_csr_aliasing | 8.670s | 2.632ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | long_msg | hmac_long_msg | 2.006m | 4.244ms | 50 | 50 | 100.00 |
| V2 | back_pressure | hmac_back_pressure | 1.084m | 1.864ms | 50 | 50 | 100.00 |
| V2 | test_vectors | hmac_test_sha_vectors | 9.359m | 125.204ms | 50 | 50 | 100.00 |
| hmac_test_hmac_vectors | 1.400s | 60.955us | 50 | 50 | 100.00 | ||
| V2 | burst_wr | hmac_burst_wr | 1.073m | 1.325ms | 50 | 50 | 100.00 |
| V2 | datapath_stress | hmac_datapath_stress | 2.527m | 5.326ms | 50 | 50 | 100.00 |
| V2 | error | hmac_error | 3.506m | 7.724ms | 50 | 50 | 100.00 |
| V2 | wipe_secret | hmac_wipe_secret | 1.785m | 11.304ms | 50 | 50 | 100.00 |
| V2 | save_and_restore | save_and_restore | 0 | 0 | -- | ||
| V2 | fifo_empty_status_interrupt | fifo_empty_status_interrupt | 0 | 0 | -- | ||
| V2 | wide_digest_configurable_key_length | wide_digest_configurable_key_length | 0 | 0 | -- | ||
| V2 | stress_all | hmac_stress_all | 33.660m | 468.947ms | 50 | 50 | 100.00 |
| V2 | alert_test | hmac_alert_test | 0.670s | 16.328us | 50 | 50 | 100.00 |
| V2 | intr_test | hmac_intr_test | 0.670s | 13.260us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | hmac_tl_errors | 4.780s | 1.027ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | hmac_tl_errors | 4.780s | 1.027ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | hmac_csr_hw_reset | 1.000s | 35.139us | 5 | 5 | 100.00 |
| hmac_csr_rw | 0.970s | 380.948us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 8.670s | 2.632ms | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 2.370s | 111.191us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | hmac_csr_hw_reset | 1.000s | 35.139us | 5 | 5 | 100.00 |
| hmac_csr_rw | 0.970s | 380.948us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 8.670s | 2.632ms | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 2.370s | 111.191us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 590 | 590 | 100.00 | |||
| V2S | tl_intg_err | hmac_sec_cm | 0.980s | 312.430us | 5 | 5 | 100.00 |
| hmac_tl_intg_err | 4.450s | 253.467us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | hmac_tl_intg_err | 4.450s | 253.467us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | write_config_and_secret_key_during_msg_wr | hmac_smoke | 7.060s | 6.312ms | 50 | 50 | 100.00 |
| V3 | stress_all_with_rand_reset | hmac_stress_all_with_rand_reset | 1.044h | 618.813ms | 15 | 200 | 7.50 |
| V3 | TOTAL | 15 | 200 | 7.50 | |||
| TOTAL | 735 | 920 | 79.89 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 16 | 13 | 13 | 81.25 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 86.94 | 92.47 | 85.27 | 100.00 | 76.32 | 85.98 | 99.49 | 69.08 |
UVM_ERROR (cip_base_vseq.sv:829) [hmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 183 failures:
0.hmac_stress_all_with_rand_reset.94885986853389795225034514710373890095404880822615371842045278241983983966
Line 39224, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 20134331313 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 20134331313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.hmac_stress_all_with_rand_reset.79274335787464541568937721706625746547576312062618954491185507426689952002119
Line 37346, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 12918851475 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 12918851475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 181 more failures.
UVM_ERROR (hmac_scoreboard.sv:289) [scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (* [*] vs * [*]) has 1 failures:
107.hmac_stress_all_with_rand_reset.106553244450352409209065416275660671924377779489491228310972435879758666659332
Line 240322, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/107.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 177824156841 ps: (hmac_scoreboard.sv:289) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (0 [0x0] vs 1403050259 [0x53a0d913])
UVM_INFO @ 177824156841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:753) [hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
117.hmac_stress_all_with_rand_reset.112181170417605607589539263732668281025141260630928300980218049036011905126978
Line 25473, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/117.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 31439772021 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 31439772021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---