ae68723071| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | hmac_smoke | 7.250s | 235.397us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | hmac_csr_hw_reset | 0.980s | 40.940us | 5 | 5 | 100.00 |
| V1 | csr_rw | hmac_csr_rw | 0.980s | 93.992us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | hmac_csr_bit_bash | 16.640s | 1.638ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | hmac_csr_aliasing | 8.740s | 539.655us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | hmac_csr_mem_rw_with_rand_reset | 12.671m | 194.957ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | hmac_csr_rw | 0.980s | 93.992us | 20 | 20 | 100.00 |
| hmac_csr_aliasing | 8.740s | 539.655us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | long_msg | hmac_long_msg | 2.382m | 15.472ms | 50 | 50 | 100.00 |
| V2 | back_pressure | hmac_back_pressure | 1.168m | 1.893ms | 50 | 50 | 100.00 |
| V2 | test_vectors | hmac_test_sha_vectors | 9.099m | 188.827ms | 50 | 50 | 100.00 |
| hmac_test_hmac_vectors | 1.400s | 278.967us | 50 | 50 | 100.00 | ||
| V2 | burst_wr | hmac_burst_wr | 1.341m | 6.166ms | 50 | 50 | 100.00 |
| V2 | datapath_stress | hmac_datapath_stress | 2.749m | 10.007ms | 50 | 50 | 100.00 |
| V2 | error | hmac_error | 4.003m | 4.327ms | 50 | 50 | 100.00 |
| V2 | wipe_secret | hmac_wipe_secret | 1.644m | 4.216ms | 50 | 50 | 100.00 |
| V2 | save_and_restore | save_and_restore | 0 | 0 | -- | ||
| V2 | fifo_empty_status_interrupt | fifo_empty_status_interrupt | 0 | 0 | -- | ||
| V2 | wide_digest_configurable_key_length | wide_digest_configurable_key_length | 0 | 0 | -- | ||
| V2 | stress_all | hmac_stress_all | 44.580m | 184.567ms | 50 | 50 | 100.00 |
| V2 | alert_test | hmac_alert_test | 0.650s | 16.105us | 50 | 50 | 100.00 |
| V2 | intr_test | hmac_intr_test | 0.680s | 22.149us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | hmac_tl_errors | 4.210s | 765.087us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | hmac_tl_errors | 4.210s | 765.087us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | hmac_csr_hw_reset | 0.980s | 40.940us | 5 | 5 | 100.00 |
| hmac_csr_rw | 0.980s | 93.992us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 8.740s | 539.655us | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 2.370s | 504.631us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | hmac_csr_hw_reset | 0.980s | 40.940us | 5 | 5 | 100.00 |
| hmac_csr_rw | 0.980s | 93.992us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 8.740s | 539.655us | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 2.370s | 504.631us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 590 | 590 | 100.00 | |||
| V2S | tl_intg_err | hmac_sec_cm | 0.980s | 525.690us | 5 | 5 | 100.00 |
| hmac_tl_intg_err | 4.000s | 250.993us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | hmac_tl_intg_err | 4.000s | 250.993us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | write_config_and_secret_key_during_msg_wr | hmac_smoke | 7.250s | 235.397us | 50 | 50 | 100.00 |
| V3 | stress_all_with_rand_reset | hmac_stress_all_with_rand_reset | 1.713h | 221.097ms | 20 | 200 | 10.00 |
| V3 | TOTAL | 20 | 200 | 10.00 | |||
| TOTAL | 740 | 920 | 80.43 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 16 | 13 | 13 | 81.25 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 86.94 | 92.47 | 85.22 | 100.00 | 76.32 | 85.98 | 99.49 | 69.08 |
UVM_ERROR (cip_base_vseq.sv:829) [hmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 178 failures:
0.hmac_stress_all_with_rand_reset.7806690249912770958608086378795993991031873334008496398279586708035074786684
Line 5699, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 21889876404 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 21889876404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.hmac_stress_all_with_rand_reset.107405310625861433670091358416089107115183151985497951739482400469473466495593
Line 33720, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 26096341785 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 26096341785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 176 more failures.
UVM_ERROR (cip_base_vseq.sv:753) [hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
76.hmac_stress_all_with_rand_reset.8254193050134279769398550368821554580469859641366539132128607556536588931599
Line 24534, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/76.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 58455379799 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 58455379799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
115.hmac_stress_all_with_rand_reset.6079989952952903198908017104768183962846600557007668243171490770580844846058
Line 1193, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/115.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 6699838762 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 6699838762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---