41bc3e0c7f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | hmac_smoke | 6.960s | 673.873us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | hmac_csr_hw_reset | 0.930s | 37.766us | 5 | 5 | 100.00 |
| V1 | csr_rw | hmac_csr_rw | 0.970s | 34.644us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | hmac_csr_bit_bash | 11.770s | 2.100ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | hmac_csr_aliasing | 7.970s | 159.072us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | hmac_csr_mem_rw_with_rand_reset | 3.475m | 159.171ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | hmac_csr_rw | 0.970s | 34.644us | 20 | 20 | 100.00 |
| hmac_csr_aliasing | 7.970s | 159.072us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | long_msg | hmac_long_msg | 2.242m | 8.649ms | 50 | 50 | 100.00 |
| V2 | back_pressure | hmac_back_pressure | 1.202m | 4.043ms | 50 | 50 | 100.00 |
| V2 | test_vectors | hmac_test_sha_vectors | 9.649m | 728.784ms | 50 | 50 | 100.00 |
| hmac_test_hmac_vectors | 1.540s | 81.291us | 50 | 50 | 100.00 | ||
| V2 | burst_wr | hmac_burst_wr | 1.333m | 6.956ms | 50 | 50 | 100.00 |
| V2 | datapath_stress | hmac_datapath_stress | 3.216m | 6.152ms | 50 | 50 | 100.00 |
| V2 | error | hmac_error | 4.198m | 28.701ms | 50 | 50 | 100.00 |
| V2 | wipe_secret | hmac_wipe_secret | 1.627m | 29.690ms | 50 | 50 | 100.00 |
| V2 | save_and_restore | save_and_restore | 0 | 0 | -- | ||
| V2 | fifo_empty_status_interrupt | fifo_empty_status_interrupt | 0 | 0 | -- | ||
| V2 | wide_digest_configurable_key_length | wide_digest_configurable_key_length | 0 | 0 | -- | ||
| V2 | stress_all | hmac_stress_all | 34.784m | 1.605s | 50 | 50 | 100.00 |
| V2 | alert_test | hmac_alert_test | 0.660s | 14.649us | 50 | 50 | 100.00 |
| V2 | intr_test | hmac_intr_test | 0.660s | 14.873us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | hmac_tl_errors | 4.570s | 273.006us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | hmac_tl_errors | 4.570s | 273.006us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | hmac_csr_hw_reset | 0.930s | 37.766us | 5 | 5 | 100.00 |
| hmac_csr_rw | 0.970s | 34.644us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 7.970s | 159.072us | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 2.520s | 117.471us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | hmac_csr_hw_reset | 0.930s | 37.766us | 5 | 5 | 100.00 |
| hmac_csr_rw | 0.970s | 34.644us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 7.970s | 159.072us | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 2.520s | 117.471us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 590 | 590 | 100.00 | |||
| V2S | tl_intg_err | hmac_sec_cm | 1.020s | 89.517us | 5 | 5 | 100.00 |
| hmac_tl_intg_err | 5.090s | 1.598ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | hmac_tl_intg_err | 5.090s | 1.598ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | write_config_and_secret_key_during_msg_wr | hmac_smoke | 6.960s | 673.873us | 50 | 50 | 100.00 |
| V3 | stress_all_with_rand_reset | hmac_stress_all_with_rand_reset | 55.553m | 83.247ms | 21 | 200 | 10.50 |
| V3 | TOTAL | 21 | 200 | 10.50 | |||
| TOTAL | 741 | 920 | 80.54 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 16 | 13 | 13 | 81.25 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 86.92 | 92.47 | 85.11 | 100.00 | 76.32 | 85.98 | 99.49 | 69.08 |
UVM_ERROR (cip_base_vseq.sv:829) [hmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 178 failures:
0.hmac_stress_all_with_rand_reset.89826486040735868424113250133060157519793202875043304845961657852506019571272
Line 266706, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 132827172965 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 132827172965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.hmac_stress_all_with_rand_reset.88677850745039644310527978264399625494697968205209518866677467515649585109764
Line 18764, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 136297283919 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 136297283919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 176 more failures.
UVM_ERROR (cip_base_vseq.sv:753) [hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
103.hmac_stress_all_with_rand_reset.2043685464399810077441330675612641704054286452748217550858964742475848416044
Line 862, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/103.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 547311303 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 547311303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---