0cb61fc7e7| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | hmac_smoke | 7.750s | 2.593ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | hmac_csr_hw_reset | 1.010s | 35.481us | 5 | 5 | 100.00 |
| V1 | csr_rw | hmac_csr_rw | 0.950s | 29.631us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | hmac_csr_bit_bash | 17.590s | 6.281ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | hmac_csr_aliasing | 8.730s | 2.311ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | hmac_csr_mem_rw_with_rand_reset | 8.964m | 72.687ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | hmac_csr_rw | 0.950s | 29.631us | 20 | 20 | 100.00 |
| hmac_csr_aliasing | 8.730s | 2.311ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | long_msg | hmac_long_msg | 2.434m | 40.080ms | 50 | 50 | 100.00 |
| V2 | back_pressure | hmac_back_pressure | 1.242m | 2.315ms | 50 | 50 | 100.00 |
| V2 | test_vectors | hmac_test_sha_vectors | 9.464m | 761.082ms | 50 | 50 | 100.00 |
| hmac_test_hmac_vectors | 1.410s | 62.534us | 50 | 50 | 100.00 | ||
| V2 | burst_wr | hmac_burst_wr | 1.098m | 3.210ms | 50 | 50 | 100.00 |
| V2 | datapath_stress | hmac_datapath_stress | 2.736m | 5.660ms | 50 | 50 | 100.00 |
| V2 | error | hmac_error | 3.749m | 159.183ms | 50 | 50 | 100.00 |
| V2 | wipe_secret | hmac_wipe_secret | 1.526m | 6.804ms | 50 | 50 | 100.00 |
| V2 | save_and_restore | save_and_restore | 0 | 0 | -- | ||
| V2 | fifo_empty_status_interrupt | fifo_empty_status_interrupt | 0 | 0 | -- | ||
| V2 | wide_digest_configurable_key_length | wide_digest_configurable_key_length | 0 | 0 | -- | ||
| V2 | stress_all | hmac_stress_all | 44.012m | 2.856s | 50 | 50 | 100.00 |
| V2 | alert_test | hmac_alert_test | 0.650s | 14.614us | 50 | 50 | 100.00 |
| V2 | intr_test | hmac_intr_test | 0.680s | 20.622us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | hmac_tl_errors | 3.950s | 344.886us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | hmac_tl_errors | 3.950s | 344.886us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | hmac_csr_hw_reset | 1.010s | 35.481us | 5 | 5 | 100.00 |
| hmac_csr_rw | 0.950s | 29.631us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 8.730s | 2.311ms | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 2.450s | 338.841us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | hmac_csr_hw_reset | 1.010s | 35.481us | 5 | 5 | 100.00 |
| hmac_csr_rw | 0.950s | 29.631us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 8.730s | 2.311ms | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 2.450s | 338.841us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 590 | 590 | 100.00 | |||
| V2S | tl_intg_err | hmac_sec_cm | 1.050s | 200.583us | 5 | 5 | 100.00 |
| hmac_tl_intg_err | 4.670s | 1.101ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | hmac_tl_intg_err | 4.670s | 1.101ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | write_config_and_secret_key_during_msg_wr | hmac_smoke | 7.750s | 2.593ms | 50 | 50 | 100.00 |
| V3 | stress_all_with_rand_reset | hmac_stress_all_with_rand_reset | 1.033h | 69.362ms | 22 | 200 | 11.00 |
| V3 | TOTAL | 22 | 200 | 11.00 | |||
| TOTAL | 742 | 920 | 80.65 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 16 | 13 | 13 | 81.25 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 87.32 | 92.47 | 85.27 | 100.00 | 78.95 | 85.98 | 99.49 | 69.08 |
UVM_ERROR (cip_base_vseq.sv:829) [hmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 178 failures:
0.hmac_stress_all_with_rand_reset.85954897201422902957477090238051662680214707990969244956354321965688835953755
Line 2414, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1873484983 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1873484983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.hmac_stress_all_with_rand_reset.81709844615435638515384980045395281912467250088348396005861445816091351021220
Line 22592, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 101428177954 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 101428177954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 176 more failures.