ecd9f08747| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | hmac_smoke | 7.100s | 2.281ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | hmac_csr_hw_reset | 0.980s | 77.155us | 5 | 5 | 100.00 |
| V1 | csr_rw | hmac_csr_rw | 0.970s | 19.489us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | hmac_csr_bit_bash | 15.420s | 2.064ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | hmac_csr_aliasing | 8.510s | 2.210ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | hmac_csr_mem_rw_with_rand_reset | 13.655m | 55.141ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | hmac_csr_rw | 0.970s | 19.489us | 20 | 20 | 100.00 |
| hmac_csr_aliasing | 8.510s | 2.210ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | long_msg | hmac_long_msg | 1.962m | 51.237ms | 50 | 50 | 100.00 |
| V2 | back_pressure | hmac_back_pressure | 1.114m | 21.735ms | 50 | 50 | 100.00 |
| V2 | test_vectors | hmac_test_sha_vectors | 8.998m | 44.481ms | 50 | 50 | 100.00 |
| hmac_test_hmac_vectors | 1.420s | 75.240us | 50 | 50 | 100.00 | ||
| V2 | burst_wr | hmac_burst_wr | 1.510m | 1.845ms | 50 | 50 | 100.00 |
| V2 | datapath_stress | hmac_datapath_stress | 2.666m | 2.786ms | 50 | 50 | 100.00 |
| V2 | error | hmac_error | 4.784m | 76.143ms | 50 | 50 | 100.00 |
| V2 | wipe_secret | hmac_wipe_secret | 1.731m | 8.726ms | 50 | 50 | 100.00 |
| V2 | save_and_restore | save_and_restore | 0 | 0 | -- | ||
| V2 | fifo_empty_status_interrupt | fifo_empty_status_interrupt | 0 | 0 | -- | ||
| V2 | wide_digest_configurable_key_length | wide_digest_configurable_key_length | 0 | 0 | -- | ||
| V2 | stress_all | hmac_stress_all | 50.395m | 296.643ms | 50 | 50 | 100.00 |
| V2 | alert_test | hmac_alert_test | 0.630s | 15.282us | 50 | 50 | 100.00 |
| V2 | intr_test | hmac_intr_test | 0.650s | 43.958us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | hmac_tl_errors | 4.050s | 209.819us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | hmac_tl_errors | 4.050s | 209.819us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | hmac_csr_hw_reset | 0.980s | 77.155us | 5 | 5 | 100.00 |
| hmac_csr_rw | 0.970s | 19.489us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 8.510s | 2.210ms | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 2.450s | 1.205ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | hmac_csr_hw_reset | 0.980s | 77.155us | 5 | 5 | 100.00 |
| hmac_csr_rw | 0.970s | 19.489us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 8.510s | 2.210ms | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 2.450s | 1.205ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 590 | 590 | 100.00 | |||
| V2S | tl_intg_err | hmac_sec_cm | 1.000s | 169.840us | 5 | 5 | 100.00 |
| hmac_tl_intg_err | 4.620s | 1.083ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | hmac_tl_intg_err | 4.620s | 1.083ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | write_config_and_secret_key_during_msg_wr | hmac_smoke | 7.100s | 2.281ms | 50 | 50 | 100.00 |
| V3 | stress_all_with_rand_reset | hmac_stress_all_with_rand_reset | 1.308h | 94.892ms | 17 | 200 | 8.50 |
| V3 | TOTAL | 17 | 200 | 8.50 | |||
| TOTAL | 737 | 920 | 80.11 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 16 | 13 | 13 | 81.25 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 86.93 | 92.47 | 85.16 | 100.00 | 76.32 | 85.98 | 99.49 | 69.08 |
UVM_ERROR (cip_base_vseq.sv:829) [hmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 180 failures:
1.hmac_stress_all_with_rand_reset.49396839840491941004337184166525851487724246117869440633849218676453451492096
Line 6495, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 28381212305 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 28381212305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.hmac_stress_all_with_rand_reset.88039156698661433352555170742778714740412193951356819759397193142712885223652
Line 20760, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3132908942 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3132908942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 178 more failures.
UVM_ERROR (cip_base_vseq.sv:753) [hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 3 failures:
116.hmac_stress_all_with_rand_reset.35300503161239821478661145877095870490183363417573592763162742615821727022030
Line 1069, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/116.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 192337004 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 192337004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
150.hmac_stress_all_with_rand_reset.51208746051800284563234426686151569162401557705658968010110586935169415651820
Line 278273, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/150.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 272394436726 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 272394436726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.