HMAC Simulation Results

Sunday May 05 2024 19:05:13 UTC

GitHub Revision: `d0c52cdadd`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 81579111587980121648949789282063322266496016209500883225240730864920651071561

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	7.680s	498.114us	50	50	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	1.020s	72.131us	5	5	100.00
V1	csr_rw	hmac_csr_rw	0.970s	31.774us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	13.300s	1.096ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	8.510s	517.182us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	28.442m	174.173ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	0.970s	31.774us	20	20	100.00
		hmac_csr_aliasing	8.510s	517.182us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	long_msg	hmac_long_msg	2.014m	8.297ms	50	50	100.00
V2	back_pressure	hmac_back_pressure	57.290s	4.079ms	50	50	100.00
V2	test_vectors	hmac_test_sha_vectors	8.593m	178.883ms	50	50	100.00
		hmac_test_hmac_vectors	1.360s	136.479us	50	50	100.00
V2	burst_wr	hmac_burst_wr	54.370s	2.887ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	2.969m	2.948ms	50	50	100.00
V2	error	hmac_error	1.993m	9.029ms	9	50	18.00
V2	wipe_secret	hmac_wipe_secret	42.700s	2.464ms	5	50	10.00
V2	save_and_restore	save_and_restore			0	0	--
V2	fifo_empty_status_interrupt	fifo_empty_status_interrupt			0	0	--
V2	wide_digest_configurable_key_length	wide_digest_configurable_key_length			0	0	--
V2	stress_all	hmac_stress_all	42.299m	1.284s	8	50	16.00
V2	alert_test	hmac_alert_test	0.660s	14.663us	50	50	100.00
V2	intr_test	hmac_intr_test	0.690s	16.693us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	4.930s	299.950us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	4.930s	299.950us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	1.020s	72.131us	5	5	100.00
		hmac_csr_rw	0.970s	31.774us	20	20	100.00
		hmac_csr_aliasing	8.510s	517.182us	5	5	100.00
		hmac_same_csr_outstanding	2.260s	649.515us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	1.020s	72.131us	5	5	100.00
		hmac_csr_rw	0.970s	31.774us	20	20	100.00
		hmac_csr_aliasing	8.510s	517.182us	5	5	100.00
		hmac_same_csr_outstanding	2.260s	649.515us	20	20	100.00
V2		TOTAL			462	590	78.31
V2S	tl_intg_err	hmac_sec_cm	0.980s	82.377us	5	5	100.00
		hmac_tl_intg_err	4.300s	1.025ms	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	4.300s	1.025ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	7.680s	498.114us	50	50	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	17.812m	20.970ms	2	200	1.00
V3		TOTAL			2	200	1.00
		TOTAL			594	920	64.57

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	16	13	10	62.50
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
87.97	95.76	94.01	100.00	65.79	91.67	99.49	69.08

Failure Buckets

Exit reason: Error: User command failed Error-[FCIBH] Illegal bin hit has 83 failures:

Test hmac_stress_all_with_rand_reset has 41 failures.

0.hmac_stress_all_with_rand_reset.38503916616230290937564073246473828954935890110051454503998439618195926681048
Line 5033, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log

  Error-[FCIBH] Illegal bin hit
  /workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv, 32
  hmac_env_pkg, "hmac_env_pkg::hmac_env_cov::err_code_cg"
    VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 47809935323 ps, Illegal
    state bin illegalvalue of coverpoint hmac_errors in covergroup

7.hmac_stress_all_with_rand_reset.34867529056232584982400287889799357980450116258498836742331689046231461559173
Line 91823, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/7.hmac_stress_all_with_rand_reset/latest/run.log

  Error-[FCIBH] Illegal bin hit
  /workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv, 32
  hmac_env_pkg, "hmac_env_pkg::hmac_env_cov::err_code_cg"
    VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 23382339590 ps, Illegal
    state bin illegalvalue of coverpoint hmac_errors in covergroup

... and 39 more failures.

Test hmac_error has 27 failures.

1.hmac_error.90829386954465784906127018366929114055083841383120321011032839477144661267409
Line 2331, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_error/latest/run.log

  Error-[FCIBH] Illegal bin hit
  /workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv, 32
  hmac_env_pkg, "hmac_env_pkg::hmac_env_cov::err_code_cg"
    VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 500086096 ps, Illegal
    state bin illegalvalue of coverpoint hmac_errors in covergroup

2.hmac_error.89081151227565758627328194016985614369084280269321683190551115101030362337266
Line 4490, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_error/latest/run.log

  Error-[FCIBH] Illegal bin hit
  /workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv, 32
  hmac_env_pkg, "hmac_env_pkg::hmac_env_cov::err_code_cg"
    VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 2211100857 ps, Illegal
    state bin illegalvalue of coverpoint hmac_errors in covergroup

... and 25 more failures.

Test hmac_stress_all has 15 failures.

2.hmac_stress_all.96256889927822429579356647154964557781432819572005230928954432992452817754786
Line 55368, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_stress_all/latest/run.log

  Error-[FCIBH] Illegal bin hit
  /workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv, 32
  hmac_env_pkg, "hmac_env_pkg::hmac_env_cov::err_code_cg"
    VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 16540830163 ps, Illegal
    state bin illegalvalue of coverpoint hmac_errors in covergroup

3.hmac_stress_all.21081511771611159126324170374045513701144861702288497012695104676980316744304
Line 2127, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/3.hmac_stress_all/latest/run.log

  Error-[FCIBH] Illegal bin hit
  /workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv, 32
  hmac_env_pkg, "hmac_env_pkg::hmac_env_cov::err_code_cg"
    VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 311698879 ps, Illegal
    state bin illegalvalue of coverpoint hmac_errors in covergroup

... and 13 more failures.

UVM_ERROR (cip_base_vseq.sv:829) [hmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 82 failures:
- Test hmac_stress_all_with_rand_reset has 82 failures.
  - 2.hmac_stress_all_with_rand_reset.85255158409264340469580767686589785379637242770883509921307989815486109560801
    Line 10446, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 65505768275 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 65505768275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.hmac_stress_all_with_rand_reset.29227216516063837690609373023155171987482190415004843656170786739945017389006
    Line 25863, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/4.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7805368561 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 7805368561 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 80 more failures.

UVM_ERROR (hmac_scoreboard.sv:331) [scoreboard] Check failed real_digest_val == exp_digest[digest_idx+*] (* [*] vs * [*]) has 36 failures:

Test hmac_stress_all has 6 failures.

1.hmac_stress_all.42463263973368990612287328224588326479844065872964475136726336925094644178036
Line 100368, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all/latest/run.log

  UVM_ERROR @ 161845083575 ps: (hmac_scoreboard.sv:331) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (1983677816 [0x763c8578] vs 3541434878 [0xd31601fe])
  UVM_INFO @ 161845083575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.hmac_stress_all.98715890659943771800521926836284203935424405094266203852871461182000875189124
Line 76213, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/6.hmac_stress_all/latest/run.log

  UVM_ERROR @ 17029612146 ps: (hmac_scoreboard.sv:331) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (2725778486 [0xa2781436] vs 1190915174 [0x46fbec66])
  UVM_INFO @ 17029612146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test hmac_wipe_secret has 11 failures.

9.hmac_wipe_secret.106100186541713900213835887747893734516113569260801308833150895567281272299100
Line 1865, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/9.hmac_wipe_secret/latest/run.log

  UVM_ERROR @ 8713309467 ps: (hmac_scoreboard.sv:331) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (4200234685 [0xfa5a7ebd] vs 7044264 [0x6b7ca8])
  UVM_INFO @ 8713309467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

11.hmac_wipe_secret.28962385626139243035719965872714987204837828824036946075781705684411673186128
Line 2127, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/11.hmac_wipe_secret/latest/run.log

  UVM_ERROR @ 5994935246 ps: (hmac_scoreboard.sv:331) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (1898802032 [0x712d6b70] vs 1012277191 [0x3c561fc7])
  UVM_INFO @ 5994935246 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 9 more failures.

Test hmac_stress_all_with_rand_reset has 19 failures.

17.hmac_stress_all_with_rand_reset.78179201541174107183980615748591842295014246404924941668488167611300784526148
Line 2872, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/17.hmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 9815670424 ps: (hmac_scoreboard.sv:331) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (1882775811 [0x7038e103] vs 3903683231 [0xe8ad7a9f])
  UVM_INFO @ 9815670424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

19.hmac_stress_all_with_rand_reset.26999546199451678348126791616435627960072332535264873724955703520493633976826
Line 2820, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/19.hmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3664345360 ps: (hmac_scoreboard.sv:331) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (3850450840 [0xe5813798] vs 4007139400 [0xeed81848])
  UVM_INFO @ 3664345360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 17 more failures.

UVM_ERROR (hmac_scoreboard.sv:321) [scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (* [*] vs * [*]) has 30 failures:

Test hmac_wipe_secret has 13 failures.

1.hmac_wipe_secret.68150874039718540900185781138269305126043501557827740160304495373169137040280
Line 274, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_wipe_secret/latest/run.log

  UVM_ERROR @  12470979 ps: (hmac_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (4051249915 [0xf1792afb] vs 223389381 [0xd50a6c5])
  UVM_INFO @  12470979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.hmac_wipe_secret.91196070945452421885892194455863347360848034575828601174117242124145732300169
Line 3586, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_wipe_secret/latest/run.log

  UVM_ERROR @ 3070975608 ps: (hmac_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (1475140231 [0x57ecda87] vs 2565043887 [0x98e376af])
  UVM_INFO @ 3070975608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 11 more failures.

Test hmac_stress_all_with_rand_reset has 15 failures.

1.hmac_stress_all_with_rand_reset.109844315725162584119070038425715534317679588649756017404098311186715211602106
Line 5556, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 25361237814 ps: (hmac_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (3224272652 [0xc02e7f0c] vs 111162270 [0x6a0339e])
  UVM_INFO @ 25361237814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

13.hmac_stress_all_with_rand_reset.55034281765418723499068848186564947592075112380432147157925159432240859040065
Line 2806, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/13.hmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4142589755 ps: (hmac_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (1515305512 [0x5a51ba28] vs 1484982863 [0x58830a4f])
  UVM_INFO @ 4142589755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 13 more failures.

Test hmac_stress_all has 2 failures.

28.hmac_stress_all.51913582819415418421807412057428248473564517334030090043640989405438751865799
Line 163386, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/28.hmac_stress_all/latest/run.log

  UVM_ERROR @ 200372467374 ps: (hmac_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (4020126199 [0xef9e41f7] vs 534329471 [0x1fd9387f])
  UVM_INFO @ 200372467374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

42.hmac_stress_all.226791613065610207418280395199475975619319586207913635083583647753333438775
Line 52858, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/42.hmac_stress_all/latest/run.log

  UVM_ERROR @ 20657146883 ps: (hmac_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (56960760 [0x36526f8] vs 496343420 [0x1d95997c])
  UVM_INFO @ 20657146883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (hmac_smoke_vseq.sv:148) [hmac_error_vseq] wait timeout occurred! has 27 failures:
- Test hmac_error has 14 failures.
  - 0.hmac_error.93077908721584166276326515837202076085353358280806906599653087072938953055503
    Line 9181, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_error/latest/run.log
```
  UVM_FATAL @ 12809290289 ps: (hmac_smoke_vseq.sv:148) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] wait timeout occurred!
  UVM_INFO @ 12809290289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.hmac_error.88912864068448358216006704957290751544134506687773456190358643784118178827576
    Line 1905, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/5.hmac_error/latest/run.log
```
  UVM_FATAL @ 11759006026 ps: (hmac_smoke_vseq.sv:148) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] wait timeout occurred!
  UVM_INFO @ 11759006026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 12 more failures.
- Test hmac_stress_all has 4 failures.
  - 4.hmac_stress_all.71235426655548695203943223000072046325480492380580931442198241193050358952865
    Line 39829, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/4.hmac_stress_all/latest/run.log
```
  UVM_FATAL @ 17959292663 ps: (hmac_smoke_vseq.sv:148) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] wait timeout occurred!
  UVM_INFO @ 17959292663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 30.hmac_stress_all.110547708841225813739844775268724138974555793590437931982648427502422830574639
    Line 263, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/30.hmac_stress_all/latest/run.log
```
  UVM_FATAL @ 10062641337 ps: (hmac_smoke_vseq.sv:148) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] wait timeout occurred!
  UVM_INFO @ 10062641337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
- Test hmac_stress_all_with_rand_reset has 9 failures.
  - 79.hmac_stress_all_with_rand_reset.82362727120172038690337619067096738127508867446387148921505064950628979673668
    Line 2181, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/79.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 15974864887 ps: (hmac_smoke_vseq.sv:148) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] wait timeout occurred!
  UVM_INFO @ 15974864887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 117.hmac_stress_all_with_rand_reset.29072954167154703285932253917346674806701325308788917907837748828424714583356
    Line 2128, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/117.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 12359014112 ps: (hmac_smoke_vseq.sv:148) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] wait timeout occurred!
  UVM_INFO @ 12359014112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

UVM_ERROR (hmac_scoreboard.sv:334) [scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (* [*] vs * [*]) has 26 failures:

Test hmac_wipe_secret has 12 failures.

0.hmac_wipe_secret.10308493445694614264112422818823171484894352747045134696335152760085588292519
Line 5059, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_wipe_secret/latest/run.log

  UVM_ERROR @ 970192451 ps: (hmac_scoreboard.sv:334) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (2723450399 [0xa2548e1f] vs 1704832013 [0x659dac0d])
  UVM_INFO @ 970192451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.hmac_wipe_secret.78096283621385878278164924257295569891899873367652201078154218409223175546555
Line 4414, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/3.hmac_wipe_secret/latest/run.log

  UVM_ERROR @ 1808351541 ps: (hmac_scoreboard.sv:334) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (1004341303 [0x3bdd0837] vs 3788040929 [0xe1c8eae1])
  UVM_INFO @ 1808351541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 10 more failures.

Test hmac_stress_all has 5 failures.

0.hmac_stress_all.97792821218684847191080851570836698404009303468280743872328959255454865008163
Line 37867, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all/latest/run.log

  UVM_ERROR @ 38640587860 ps: (hmac_scoreboard.sv:334) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (2810724912 [0xa7884230] vs 2297737797 [0x88f4b245])
  UVM_INFO @ 38640587860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.hmac_stress_all.98981845982018010650893906302571791976063427820723710382093601676624641832129
Line 1161, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/5.hmac_stress_all/latest/run.log

  UVM_ERROR @ 247621114 ps: (hmac_scoreboard.sv:334) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (4261497650 [0xfe014b32] vs 776001986 [0x2e40d9c2])
  UVM_INFO @ 247621114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test hmac_stress_all_with_rand_reset has 9 failures.

18.hmac_stress_all_with_rand_reset.104489029469145126974731554530928558794745330399931397289859126296157748205314
Line 2708, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/18.hmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 264354627 ps: (hmac_scoreboard.sv:334) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (458524496 [0x1b548750] vs 1230861022 [0x495d72de])
  UVM_INFO @ 264354627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

23.hmac_stress_all_with_rand_reset.93408405965425819090093782764965548012989731291521007672110378149992738829491
Line 18343, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/23.hmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2924897756 ps: (hmac_scoreboard.sv:334) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (2157978065 [0x80a021d1] vs 4138493107 [0xf6ac64b3])
  UVM_INFO @ 2924897756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

UVM_ERROR (hmac_scoreboard.sv:318) [scoreboard] Check failed real_digest_val == exp_digest[digest_idx+*] (* [*] vs * [*]) has 20 failures:

Test hmac_stress_all_with_rand_reset has 8 failures.

3.hmac_stress_all_with_rand_reset.26685643440384838110275288107096471699261493129083589209715644024780795589363
Line 7413, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/3.hmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3702094232 ps: (hmac_scoreboard.sv:318) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (3652519713 [0xd9b50721] vs 920019749 [0x36d66325])
  UVM_INFO @ 3702094232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

47.hmac_stress_all_with_rand_reset.79917926749061342473338159721850578461063000480184836204813448234601546620644
Line 73447, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/47.hmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 21117168028 ps: (hmac_scoreboard.sv:318) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (3086362481 [0xb7f62771] vs 4170195371 [0xf89021ab])
  UVM_INFO @ 21117168028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Test hmac_wipe_secret has 9 failures.

13.hmac_wipe_secret.96670589003103869488521670086120108791353216779393796180437781642702903829047
Line 343, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/13.hmac_wipe_secret/latest/run.log

  UVM_ERROR @  54005676 ps: (hmac_scoreboard.sv:318) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (1871076025 [0x6f865ab9] vs 1693910544 [0x64f70610])
  UVM_INFO @  54005676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

17.hmac_wipe_secret.96606808750182787271211951250879444746906396409635175325586130521105787372768
Line 2104, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/17.hmac_wipe_secret/latest/run.log

  UVM_ERROR @ 2405123200 ps: (hmac_scoreboard.sv:318) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (521566020 [0x1f167744] vs 2283879093 [0x88213ab5])
  UVM_INFO @ 2405123200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

Test hmac_stress_all has 3 failures.

31.hmac_stress_all.1173482877740349516763429489325938075559434228518950899399399045970640087216
Line 48936, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/31.hmac_stress_all/latest/run.log

  UVM_ERROR @ 12723095262 ps: (hmac_scoreboard.sv:318) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (4010017249 [0xef0401e1] vs 784703056 [0x2ec59e50])
  UVM_INFO @ 12723095262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

33.hmac_stress_all.26989324558954111608727558690151597784232553884192713694845881661931454679849
Line 239438, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/33.hmac_stress_all/latest/run.log

  UVM_ERROR @ 125179851617 ps: (hmac_scoreboard.sv:318) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (740785729 [0x2c277e41] vs 3910323820 [0xe912ce6c])
  UVM_INFO @ 125179851617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (hmac_scoreboard.sv:297) [scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (* [*] vs * [*]) has 10 failures:
- Test hmac_stress_all has 3 failures.
  - 9.hmac_stress_all.110761901099553301109423979758522319216018962850477897105508531598718578313435
    Line 181228, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/9.hmac_stress_all/latest/run.log
```
  UVM_ERROR @ 16000524288 ps: (hmac_scoreboard.sv:297) [uvm_test_top.env.scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (0 [0x0] vs 0 [0x0])
  UVM_INFO @ 16000524288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 29.hmac_stress_all.49204022057369208042345812384828566494867032196068350580228798667281989270689
    Line 79202, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/29.hmac_stress_all/latest/run.log
```
  UVM_ERROR @ 40279180676 ps: (hmac_scoreboard.sv:297) [uvm_test_top.env.scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (0 [0x0] vs 0 [0x0])
  UVM_INFO @ 40279180676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test hmac_stress_all_with_rand_reset has 7 failures.
  - 86.hmac_stress_all_with_rand_reset.42079088241144571495704688909647173402246783374620209589092345774558987786417
    Line 631, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/86.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 786403750 ps: (hmac_scoreboard.sv:297) [uvm_test_top.env.scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (0 [0x0] vs 0 [0x0])
  UVM_INFO @ 786403750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 90.hmac_stress_all_with_rand_reset.15293451896751162758804386878252448586100652276404066874847866966850528079352
    Line 5380, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/90.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 14280088342 ps: (hmac_scoreboard.sv:297) [uvm_test_top.env.scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (0 [0x0] vs 0 [0x0])
  UVM_INFO @ 14280088342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=*) == * has 7 failures:
- Test hmac_stress_all has 3 failures.
  - 34.hmac_stress_all.36281518499491645578026433909299796349843203075599141841828567694772180557681
    Line 149141, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/34.hmac_stress_all/latest/run.log
```
  UVM_FATAL @ 43181941878 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=0xf3d12000) == 0x1
  UVM_INFO @ 43181941878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 41.hmac_stress_all.4323727041130155434180471755180542722601420076362111454560380121069420294785
    Line 97108, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/41.hmac_stress_all/latest/run.log
```
  UVM_FATAL @ 213020834367 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=0xff20000) == 0x1
  UVM_INFO @ 213020834367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test hmac_stress_all_with_rand_reset has 4 failures.
  - 64.hmac_stress_all_with_rand_reset.72182536915371816904647604935914945205108406760320846867013672982453512789595
    Line 39734, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/64.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 22216692270 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=0xe8604000) == 0x1
  UVM_INFO @ 22216692270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 139.hmac_stress_all_with_rand_reset.32714875983551203157803437307696951031227271119898854932560001075151491573470
    Line 30096, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/139.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 28986876374 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=0x473ee000) == 0x1
  UVM_INFO @ 28986876374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_ERROR (hmac_scoreboard.sv:309) [scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (* [*] vs * [*]) has 4 failures:
- Test hmac_stress_all_with_rand_reset has 3 failures.
  - 44.hmac_stress_all_with_rand_reset.114557759966537514023860785901149620091357884905694225122203194962085091964966
    Line 6639, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/44.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 87021411311 ps: (hmac_scoreboard.sv:309) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (0 [0x0] vs 3334963259 [0xc6c7803b])
  UVM_INFO @ 87021411311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 78.hmac_stress_all_with_rand_reset.33545113975945133916143645588627072850387865621990414602575324573990039911523
    Line 10687, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/78.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 27611415966 ps: (hmac_scoreboard.sv:309) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (0 [0x0] vs 2486636488 [0x94370fc8])
  UVM_INFO @ 27611415966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test hmac_stress_all has 1 failures.
  - 48.hmac_stress_all.60045030263458782021922586902651037471589412197279141667683148757826010524335
    Line 3858, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/48.hmac_stress_all/latest/run.log
```
  UVM_ERROR @ 4664398874 ps: (hmac_scoreboard.sv:309) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (0 [0x0] vs 939102447 [0x37f990ef])
  UVM_INFO @ 4664398874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:753) [hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test hmac_stress_all_with_rand_reset has 1 failures.
  - 102.hmac_stress_all_with_rand_reset.85550235997886227323288705247009451985377490564838591674665794760074302369804
    Line 290, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/102.hmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 360551195 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 360551195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```