HMAC Simulation Results

Sunday May 05 2024 19:05:13 UTC

GitHub Revision: d0c52cdadd

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 81579111587980121648949789282063322266496016209500883225240730864920651071561

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 7.680s 498.114us 50 50 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.020s 72.131us 5 5 100.00
V1 csr_rw hmac_csr_rw 0.970s 31.774us 20 20 100.00
V1 csr_bit_bash hmac_csr_bit_bash 13.300s 1.096ms 5 5 100.00
V1 csr_aliasing hmac_csr_aliasing 8.510s 517.182us 5 5 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 28.442m 174.173ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.970s 31.774us 20 20 100.00
hmac_csr_aliasing 8.510s 517.182us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 long_msg hmac_long_msg 2.014m 8.297ms 50 50 100.00
V2 back_pressure hmac_back_pressure 57.290s 4.079ms 50 50 100.00
V2 test_vectors hmac_test_sha_vectors 8.593m 178.883ms 50 50 100.00
hmac_test_hmac_vectors 1.360s 136.479us 50 50 100.00
V2 burst_wr hmac_burst_wr 54.370s 2.887ms 50 50 100.00
V2 datapath_stress hmac_datapath_stress 2.969m 2.948ms 50 50 100.00
V2 error hmac_error 1.993m 9.029ms 9 50 18.00
V2 wipe_secret hmac_wipe_secret 42.700s 2.464ms 5 50 10.00
V2 save_and_restore save_and_restore 0 0 --
V2 fifo_empty_status_interrupt fifo_empty_status_interrupt 0 0 --
V2 wide_digest_configurable_key_length wide_digest_configurable_key_length 0 0 --
V2 stress_all hmac_stress_all 42.299m 1.284s 8 50 16.00
V2 alert_test hmac_alert_test 0.660s 14.663us 50 50 100.00
V2 intr_test hmac_intr_test 0.690s 16.693us 50 50 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 4.930s 299.950us 20 20 100.00
V2 tl_d_illegal_access hmac_tl_errors 4.930s 299.950us 20 20 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.020s 72.131us 5 5 100.00
hmac_csr_rw 0.970s 31.774us 20 20 100.00
hmac_csr_aliasing 8.510s 517.182us 5 5 100.00
hmac_same_csr_outstanding 2.260s 649.515us 20 20 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.020s 72.131us 5 5 100.00
hmac_csr_rw 0.970s 31.774us 20 20 100.00
hmac_csr_aliasing 8.510s 517.182us 5 5 100.00
hmac_same_csr_outstanding 2.260s 649.515us 20 20 100.00
V2 TOTAL 462 590 78.31
V2S tl_intg_err hmac_sec_cm 0.980s 82.377us 5 5 100.00
hmac_tl_intg_err 4.300s 1.025ms 20 20 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 4.300s 1.025ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 7.680s 498.114us 50 50 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 17.812m 20.970ms 2 200 1.00
V3 TOTAL 2 200 1.00
TOTAL 594 920 64.57

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 16 13 10 62.50
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
87.97 95.76 94.01 100.00 65.79 91.67 99.49 69.08

Failure Buckets

Past Results