18c8953cf1| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | hmac_smoke | 6.750s | 3.982ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | hmac_csr_hw_reset | 0.990s | 42.458us | 5 | 5 | 100.00 |
| V1 | csr_rw | hmac_csr_rw | 0.960s | 47.095us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | hmac_csr_bit_bash | 16.470s | 2.250ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | hmac_csr_aliasing | 7.840s | 609.853us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | hmac_csr_mem_rw_with_rand_reset | 15.945m | 91.870ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | hmac_csr_rw | 0.960s | 47.095us | 20 | 20 | 100.00 |
| hmac_csr_aliasing | 7.840s | 609.853us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | long_msg | hmac_long_msg | 2.236m | 9.479ms | 50 | 50 | 100.00 |
| V2 | back_pressure | hmac_back_pressure | 1.107m | 1.155ms | 50 | 50 | 100.00 |
| V2 | test_vectors | hmac_test_sha_vectors | 9.676m | 184.034ms | 50 | 50 | 100.00 |
| hmac_test_hmac_vectors | 1.350s | 288.464us | 50 | 50 | 100.00 | ||
| V2 | burst_wr | hmac_burst_wr | 56.370s | 1.417ms | 50 | 50 | 100.00 |
| V2 | datapath_stress | hmac_datapath_stress | 2.834m | 11.467ms | 50 | 50 | 100.00 |
| V2 | error | hmac_error | 1.679m | 10.264ms | 5 | 50 | 10.00 |
| V2 | wipe_secret | hmac_wipe_secret | 33.500s | 4.944ms | 4 | 50 | 8.00 |
| V2 | save_and_restore | save_and_restore | 0 | 0 | -- | ||
| V2 | fifo_empty_status_interrupt | fifo_empty_status_interrupt | 0 | 0 | -- | ||
| V2 | wide_digest_configurable_key_length | wide_digest_configurable_key_length | 0 | 0 | -- | ||
| V2 | stress_all | hmac_stress_all | 16.456m | 295.893ms | 8 | 50 | 16.00 |
| V2 | alert_test | hmac_alert_test | 0.720s | 61.267us | 50 | 50 | 100.00 |
| V2 | intr_test | hmac_intr_test | 0.650s | 28.302us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | hmac_tl_errors | 4.420s | 479.873us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | hmac_tl_errors | 4.420s | 479.873us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | hmac_csr_hw_reset | 0.990s | 42.458us | 5 | 5 | 100.00 |
| hmac_csr_rw | 0.960s | 47.095us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 7.840s | 609.853us | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 2.710s | 1.911ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | hmac_csr_hw_reset | 0.990s | 42.458us | 5 | 5 | 100.00 |
| hmac_csr_rw | 0.960s | 47.095us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 7.840s | 609.853us | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 2.710s | 1.911ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 457 | 590 | 77.46 | |||
| V2S | tl_intg_err | hmac_sec_cm | 1.020s | 95.150us | 5 | 5 | 100.00 |
| hmac_tl_intg_err | 4.490s | 365.786us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | hmac_tl_intg_err | 4.490s | 365.786us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | write_config_and_secret_key_during_msg_wr | hmac_smoke | 6.750s | 3.982ms | 50 | 50 | 100.00 |
| V3 | stress_all_with_rand_reset | hmac_stress_all_with_rand_reset | 22.265m | 48.444ms | 1 | 200 | 0.50 |
| V3 | TOTAL | 1 | 200 | 0.50 | |||
| TOTAL | 588 | 920 | 63.91 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 16 | 13 | 10 | 62.50 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 87.97 | 95.76 | 94.01 | 100.00 | 65.79 | 91.67 | 99.49 | 69.08 |
UVM_ERROR (cip_base_vseq.sv:829) [hmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 86 failures:
3.hmac_stress_all_with_rand_reset.25634819767663137486727130432896592194084068750608454135654236699387774948194
Line 5240, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/3.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4184604686 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 4184604686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.hmac_stress_all_with_rand_reset.42592269998968827337137423295491115050909709012375094673432105358926911036645
Line 3691, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/4.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 16476796686 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 16476796686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 84 more failures.
Exit reason: Error: User command failed Error-[FCIBH] Illegal bin hit has 79 failures:
0.hmac_stress_all.47254184035319227997433513434271677266063659181550983642777708018306182685630
Line 10908, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all/latest/run.log
Error-[FCIBH] Illegal bin hit
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv, 32
hmac_env_pkg, "hmac_env_pkg::hmac_env_cov::err_code_cg"
VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 4042870112 ps, Illegal
state bin illegalvalue of coverpoint hmac_errors in covergroup
3.hmac_stress_all.38240703713504859095746218349888066286118545080306250672932805462058083175187
Line 1663, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/3.hmac_stress_all/latest/run.log
Error-[FCIBH] Illegal bin hit
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv, 32
hmac_env_pkg, "hmac_env_pkg::hmac_env_cov::err_code_cg"
VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 1182706277 ps, Illegal
state bin illegalvalue of coverpoint hmac_errors in covergroup
... and 9 more failures.
2.hmac_error.98820825465578225370403685838607590110491492559528037057810884629488955961154
Line 4041, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_error/latest/run.log
Error-[FCIBH] Illegal bin hit
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv, 32
hmac_env_pkg, "hmac_env_pkg::hmac_env_cov::err_code_cg"
VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 1153283995 ps, Illegal
state bin illegalvalue of coverpoint hmac_errors in covergroup
3.hmac_error.93989440789639684386981317173705582687522556555220430746137537779130764218733
Line 258, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/3.hmac_error/latest/run.log
Error-[FCIBH] Illegal bin hit
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv, 32
hmac_env_pkg, "hmac_env_pkg::hmac_env_cov::err_code_cg"
VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 5072693 ps, Illegal state
bin illegalvalue of coverpoint hmac_errors in covergroup
... and 25 more failures.
2.hmac_stress_all_with_rand_reset.83390404383736269791498717420791515220203900588964419952929435656663452108795
Line 18412, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_stress_all_with_rand_reset/latest/run.log
Error-[FCIBH] Illegal bin hit
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv, 32
hmac_env_pkg, "hmac_env_pkg::hmac_env_cov::err_code_cg"
VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 1399495178 ps, Illegal
state bin illegalvalue of coverpoint hmac_errors in covergroup
7.hmac_stress_all_with_rand_reset.71747927977488442122412716873340764735431647396015413015353564890078160677678
Line 12915, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/7.hmac_stress_all_with_rand_reset/latest/run.log
Error-[FCIBH] Illegal bin hit
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv, 32
hmac_env_pkg, "hmac_env_pkg::hmac_env_cov::err_code_cg"
VERIFICATION ERROR (FUNCTIONAL COVERAGE) : At time 4651420435 ps, Illegal
state bin illegalvalue of coverpoint hmac_errors in covergroup
... and 39 more failures.
UVM_ERROR (hmac_scoreboard.sv:334) [scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (* [*] vs * [*]) has 33 failures:
0.hmac_stress_all_with_rand_reset.13982838328430683448393925056324079622154842368822567938057107477332264267923
Line 949, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 6971757502 ps: (hmac_scoreboard.sv:334) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (2501808649 [0x951e9209] vs 1254801130 [0x4acabeea])
UVM_INFO @ 6971757502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.hmac_stress_all_with_rand_reset.47995849126325970847554164599964166191137169528310627866476250680287078483887
Line 17270, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/9.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 10996291345 ps: (hmac_scoreboard.sv:334) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (1486442762 [0x5899510a] vs 3295140615 [0xc467db07])
UVM_INFO @ 10996291345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 15 more failures.
2.hmac_wipe_secret.99613363236580367656792245436710422532318333549389864449583000529521970924238
Line 2257, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_wipe_secret/latest/run.log
UVM_ERROR @ 720929156 ps: (hmac_scoreboard.sv:334) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (2615921429 [0x9bebcb15] vs 2808131640 [0xa760b038])
UVM_INFO @ 720929156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.hmac_wipe_secret.54760612350428733207901980874115063417653151184158351427094528393560950720371
Line 1986, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/4.hmac_wipe_secret/latest/run.log
UVM_ERROR @ 311685818 ps: (hmac_scoreboard.sv:334) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (1677855794 [0x64020c32] vs 1133989890 [0x43975002])
UVM_INFO @ 311685818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.
5.hmac_stress_all.99226814788399859152457608748112118026109160351383311583631339605864032551552
Line 5220, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/5.hmac_stress_all/latest/run.log
UVM_ERROR @ 1036242579 ps: (hmac_scoreboard.sv:334) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (2425092717 [0x908bfa6d] vs 4196750101 [0xfa255315])
UVM_INFO @ 1036242579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.hmac_stress_all.56909144008400659337619047655175418928533881095652725947569932208266097857643
Line 9334, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/14.hmac_stress_all/latest/run.log
UVM_ERROR @ 2381410466 ps: (hmac_scoreboard.sv:334) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (2570606055 [0x993855e7] vs 1421867600 [0x54bffa50])
UVM_INFO @ 2381410466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (hmac_scoreboard.sv:321) [scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (* [*] vs * [*]) has 31 failures:
4.hmac_stress_all.107152256645155035093625967389126227629797123437317645049648489909666435758120
Line 19080, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/4.hmac_stress_all/latest/run.log
UVM_ERROR @ 4110083825 ps: (hmac_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (4259499031 [0xfde2cc17] vs 921870570 [0x36f2a0ea])
UVM_INFO @ 4110083825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.hmac_stress_all.107339623836654693114632642007816349702265176674272756490417135885655941151071
Line 35387, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/6.hmac_stress_all/latest/run.log
UVM_ERROR @ 11814019101 ps: (hmac_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (4127205971 [0xf6002a53] vs 391218471 [0x17518527])
UVM_INFO @ 11814019101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
6.hmac_wipe_secret.25398470499584415537693900842308218679326787186634020548475575313937881767934
Line 7899, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/6.hmac_wipe_secret/latest/run.log
UVM_ERROR @ 411915636 ps: (hmac_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (1560862253 [0x5d08de2d] vs 895107618 [0x355a4222])
UVM_INFO @ 411915636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.hmac_wipe_secret.3023251750294453891399642156433421923379160002808145016660101409816639554723
Line 3473, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/14.hmac_wipe_secret/latest/run.log
UVM_ERROR @ 1356652096 ps: (hmac_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (1702043662 [0x6573200e] vs 966893644 [0x39a1a04c])
UVM_INFO @ 1356652096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.
17.hmac_stress_all_with_rand_reset.100301011913232833420235040369904112408981023139728584396850089646599132330381
Line 2685, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/17.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 6545628319 ps: (hmac_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (3890880220 [0xe7ea1edc] vs 341953386 [0x1461cb6a])
UVM_INFO @ 6545628319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
38.hmac_stress_all_with_rand_reset.112175856959112840625548294754118995484063874698100138160953987877522146670766
Line 5574, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/38.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7609980215 ps: (hmac_scoreboard.sv:321) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (802241195 [0x2fd13aab] vs 3503653129 [0xd0d58109])
UVM_INFO @ 7609980215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
UVM_ERROR (hmac_scoreboard.sv:331) [scoreboard] Check failed real_digest_val == exp_digest[digest_idx+*] (* [*] vs * [*]) has 30 failures:
5.hmac_wipe_secret.84795759300545952318788539124553304466415874593919498083744870613843154952499
Line 792, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/5.hmac_wipe_secret/latest/run.log
UVM_ERROR @ 118164024 ps: (hmac_scoreboard.sv:331) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (3438426063 [0xccf237cf] vs 3556463818 [0xd3fb54ca])
UVM_INFO @ 118164024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.hmac_wipe_secret.83379492369047493104209905013178774074535822397909707120018991723548789313745
Line 1615, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/7.hmac_wipe_secret/latest/run.log
UVM_ERROR @ 151339490 ps: (hmac_scoreboard.sv:331) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (2466697186 [0x9306cfe2] vs 126792329 [0x78eb289])
UVM_INFO @ 151339490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
7.hmac_stress_all.56955146839287094373967588137709771673494607464519336822748989834316602776687
Line 25896, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/7.hmac_stress_all/latest/run.log
UVM_ERROR @ 5788881490 ps: (hmac_scoreboard.sv:331) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (1282288024 [0x4c6e2998] vs 1719750501 [0x66814f65])
UVM_INFO @ 5788881490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.hmac_stress_all.114135100410856026651318476198162517569129228599660967706411008214147694898562
Line 1528, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/8.hmac_stress_all/latest/run.log
UVM_ERROR @ 350932142 ps: (hmac_scoreboard.sv:331) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (436339698 [0x1a0203f2] vs 3736419505 [0xdeb53cb1])
UVM_INFO @ 350932142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
19.hmac_stress_all_with_rand_reset.91668475561914575836901346757147155176291877676553455070163176722953848582974
Line 95009, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/19.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 6032437803 ps: (hmac_scoreboard.sv:331) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (3962534948 [0xec2f7c24] vs 2844490784 [0xa98b7c20])
UVM_INFO @ 6032437803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.hmac_stress_all_with_rand_reset.82448567039022763557457920578401931024644249114648422602401010908397883677958
Line 68224, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/20.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 68194752785 ps: (hmac_scoreboard.sv:331) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (3038632633 [0xb51ddab9] vs 2078127205 [0x7bddb465])
UVM_INFO @ 68194752785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
UVM_FATAL (hmac_smoke_vseq.sv:148) [hmac_error_vseq] wait timeout occurred! has 27 failures:
0.hmac_error.29359529442276101973049405941316656648351687341428022822670815883762647075063
Line 3791, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_error/latest/run.log
UVM_FATAL @ 11705410408 ps: (hmac_smoke_vseq.sv:148) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] wait timeout occurred!
UVM_INFO @ 11705410408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.hmac_error.72146876422569678181544285170572249881154037238729670562070365353424261528542
Line 4760, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_error/latest/run.log
UVM_FATAL @ 14995339682 ps: (hmac_smoke_vseq.sv:148) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] wait timeout occurred!
UVM_INFO @ 14995339682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
2.hmac_stress_all.62275509866216706451356776050466778238758308204624597219202545926215927936126
Line 81788, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_stress_all/latest/run.log
UVM_FATAL @ 271030116192 ps: (hmac_smoke_vseq.sv:148) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] wait timeout occurred!
UVM_INFO @ 271030116192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
21.hmac_stress_all.72810634056077617151561404721579540325489866445153726502849083806043392740553
Line 120634, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/21.hmac_stress_all/latest/run.log
UVM_FATAL @ 196294186320 ps: (hmac_smoke_vseq.sv:148) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] wait timeout occurred!
UVM_INFO @ 196294186320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
18.hmac_stress_all_with_rand_reset.97641733582733548910202125530750385745854569367879819904973972249083756591690
Line 16208, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/18.hmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 59253221412 ps: (hmac_smoke_vseq.sv:148) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] wait timeout occurred!
UVM_INFO @ 59253221412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
22.hmac_stress_all_with_rand_reset.105532923471683801202927219434857025922651213510323254888996091357719071411145
Line 37303, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/22.hmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 25507662042 ps: (hmac_smoke_vseq.sv:148) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] wait timeout occurred!
UVM_INFO @ 25507662042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (hmac_scoreboard.sv:318) [scoreboard] Check failed real_digest_val == exp_digest[digest_idx+*] (* [*] vs * [*]) has 27 failures:
Test hmac_wipe_secret has 12 failures.
0.hmac_wipe_secret.17233922156537153045238313964716057306597099013888194366777310085664697593766
Line 1699, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_wipe_secret/latest/run.log
UVM_ERROR @ 259113878 ps: (hmac_scoreboard.sv:318) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (141669305 [0x871b3b9] vs 3412417938 [0xcb655d92])
UVM_INFO @ 259113878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.hmac_wipe_secret.110699965909359806692237922177530552141757057331737989442207342936682780822082
Line 2053, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/10.hmac_wipe_secret/latest/run.log
UVM_ERROR @ 310179643 ps: (hmac_scoreboard.sv:318) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (1716095907 [0x66498ba3] vs 617328089 [0x24cbadd9])
UVM_INFO @ 310179643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
Test hmac_error has 1 failures.
4.hmac_error.79779397447671336124969418161045787883302390834280234388559522508237405545350
Line 7269, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/4.hmac_error/latest/run.log
UVM_ERROR @ 2265573074 ps: (hmac_scoreboard.sv:318) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (0 [0x0] vs 354298151 [0x151e2927])
UVM_INFO @ 2265573074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test hmac_stress_all has 1 failures.
9.hmac_stress_all.54135303354889570042422978539759063871001902821249495785116053825808940363885
Line 2994, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/9.hmac_stress_all/latest/run.log
UVM_ERROR @ 294879866 ps: (hmac_scoreboard.sv:318) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (1671662948 [0x63a38d64] vs 939754308 [0x38038344])
UVM_INFO @ 294879866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test hmac_stress_all_with_rand_reset has 13 failures.
26.hmac_stress_all_with_rand_reset.39648676877232702379106379295182486107654188353214034608481594539308579411479
Line 39211, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/26.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2899440711 ps: (hmac_scoreboard.sv:318) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (4015023984 [0xef506770] vs 3866200477 [0xe671899d])
UVM_INFO @ 2899440711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
72.hmac_stress_all_with_rand_reset.10722149086310161184591495919302761485033424177531369456690436895013017561747
Line 18314, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/72.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 36156677968 ps: (hmac_scoreboard.sv:318) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (3318301978 [0xc5c9451a] vs 0 [0x0])
UVM_INFO @ 36156677968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=*) == * has 9 failures:
1.hmac_stress_all_with_rand_reset.19203823457389218738823445409162938266757604726313468977825868933033667278440
Line 12046, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 28233328017 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=0x874c4000) == 0x1
UVM_INFO @ 28233328017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
179.hmac_stress_all_with_rand_reset.57833838755546225609884800563399520520234377512141701644030221192283928987265
Line 33301, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/179.hmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 136208433817 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=0xa6120000) == 0x1
UVM_INFO @ 136208433817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
20.hmac_stress_all.112154811802402887630143294360016460573014183356250272257041830070914363647585
Line 14157, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/20.hmac_stress_all/latest/run.log
UVM_FATAL @ 14560178350 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=0x2b154000) == 0x1
UVM_INFO @ 14560178350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
29.hmac_stress_all.12650858306639092218775895007243819050281409017182155999273179438677228465577
Line 3446, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/29.hmac_stress_all/latest/run.log
UVM_FATAL @ 10463184650 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=0x5a4d8000) == 0x1
UVM_INFO @ 10463184650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
28.hmac_error.11938285368875882455341190759875893336829440446351204476727129727959249529052
Line 14496, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/28.hmac_error/latest/run.log
UVM_FATAL @ 34750455555 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=0xff5a0000) == 0x1
UVM_INFO @ 34750455555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
48.hmac_error.105367073062064396941924497266929781344908592651169578853612334479181375641698
Line 749, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/48.hmac_error/latest/run.log
UVM_FATAL @ 10623615599 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=0xe2a74000) == 0x1
UVM_INFO @ 10623615599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (hmac_scoreboard.sv:297) [scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (* [*] vs * [*]) has 8 failures:
Test hmac_stress_all has 2 failures.
15.hmac_stress_all.19569049708533492227659363641687037548888088509000113301368265069944906061648
Line 176950, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/15.hmac_stress_all/latest/run.log
UVM_ERROR @ 295892649408 ps: (hmac_scoreboard.sv:297) [uvm_test_top.env.scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (0 [0x0] vs 0 [0x0])
UVM_INFO @ 295892649408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
35.hmac_stress_all.69322116194146997637393351055472533543069552548849467213730872446738962772964
Line 24972, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/35.hmac_stress_all/latest/run.log
UVM_ERROR @ 6688367290 ps: (hmac_scoreboard.sv:297) [uvm_test_top.env.scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (0 [0x0] vs 0 [0x0])
UVM_INFO @ 6688367290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test hmac_stress_all_with_rand_reset has 6 failures.
45.hmac_stress_all_with_rand_reset.88309968580444929934222574469722347391550818227374114427738881769106637123769
Line 1715, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/45.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 868627852 ps: (hmac_scoreboard.sv:297) [uvm_test_top.env.scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (0 [0x0] vs 0 [0x0])
UVM_INFO @ 868627852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
55.hmac_stress_all_with_rand_reset.48588656772430551369477476961425570293386683171210523217346477074543433118165
Line 1640, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/55.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 8330341068 ps: (hmac_scoreboard.sv:297) [uvm_test_top.env.scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (0 [0x0] vs 0 [0x0])
UVM_INFO @ 8330341068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_ERROR (hmac_scoreboard.sv:609) [scoreboard] Check failed cfg.hmac_vif.is_idle() == val (* [*] vs * [*]) has 1 failures:
19.hmac_stress_all.88092201169374613146362416450031879824756019910815907729303496588836022093836
Line 53703, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/19.hmac_stress_all/latest/run.log
UVM_ERROR @ 15393388790 ps: (hmac_scoreboard.sv:609) [uvm_test_top.env.scoreboard] Check failed cfg.hmac_vif.is_idle() == val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 15393388790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:753) [hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
165.hmac_stress_all_with_rand_reset.89242003439798714510763866178520485835573741216443447655448291374466414841897
Line 18928, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/165.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 25557487965 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 25557487965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---