9656691e03| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | hmac_smoke | 7.000s | 614.833us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | hmac_csr_hw_reset | 1.030s | 22.178us | 5 | 5 | 100.00 |
| V1 | csr_rw | hmac_csr_rw | 0.940s | 119.862us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | hmac_csr_bit_bash | 15.840s | 1.101ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | hmac_csr_aliasing | 8.560s | 1.783ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | hmac_csr_mem_rw_with_rand_reset | 10.398m | 40.860ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | hmac_csr_rw | 0.940s | 119.862us | 20 | 20 | 100.00 |
| hmac_csr_aliasing | 8.560s | 1.783ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | long_msg | hmac_long_msg | 2.171m | 15.253ms | 50 | 50 | 100.00 |
| V2 | back_pressure | hmac_back_pressure | 59.560s | 4.625ms | 50 | 50 | 100.00 |
| V2 | test_vectors | hmac_test_sha_vectors | 9.550m | 87.850ms | 50 | 50 | 100.00 |
| hmac_test_hmac_vectors | 1.410s | 75.387us | 50 | 50 | 100.00 | ||
| V2 | burst_wr | hmac_burst_wr | 1.351m | 4.573ms | 50 | 50 | 100.00 |
| V2 | datapath_stress | hmac_datapath_stress | 20.767m | 28.956ms | 50 | 50 | 100.00 |
| V2 | error | hmac_error | 7.232m | 10.444ms | 12 | 50 | 24.00 |
| V2 | wipe_secret | hmac_wipe_secret | 33.820s | 897.424us | 4 | 50 | 8.00 |
| V2 | save_and_restore | save_and_restore | 0 | 0 | -- | ||
| V2 | fifo_empty_status_interrupt | fifo_empty_status_interrupt | 0 | 0 | -- | ||
| V2 | wide_digest_configurable_key_length | wide_digest_configurable_key_length | 0 | 0 | -- | ||
| V2 | stress_all | hmac_stress_all | 45.439m | 36.733ms | 12 | 50 | 24.00 |
| V2 | alert_test | hmac_alert_test | 0.660s | 23.643us | 50 | 50 | 100.00 |
| V2 | intr_test | hmac_intr_test | 0.660s | 16.365us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | hmac_tl_errors | 3.990s | 147.316us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | hmac_tl_errors | 3.990s | 147.316us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | hmac_csr_hw_reset | 1.030s | 22.178us | 5 | 5 | 100.00 |
| hmac_csr_rw | 0.940s | 119.862us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 8.560s | 1.783ms | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 2.400s | 735.458us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | hmac_csr_hw_reset | 1.030s | 22.178us | 5 | 5 | 100.00 |
| hmac_csr_rw | 0.940s | 119.862us | 20 | 20 | 100.00 | ||
| hmac_csr_aliasing | 8.560s | 1.783ms | 5 | 5 | 100.00 | ||
| hmac_same_csr_outstanding | 2.400s | 735.458us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 468 | 590 | 79.32 | |||
| V2S | tl_intg_err | hmac_sec_cm | 0.990s | 83.334us | 5 | 5 | 100.00 |
| hmac_tl_intg_err | 4.440s | 243.615us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | hmac_tl_intg_err | 4.440s | 243.615us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | write_config_and_secret_key_during_msg_wr | hmac_smoke | 7.000s | 614.833us | 50 | 50 | 100.00 |
| V3 | stress_all_with_rand_reset | hmac_stress_all_with_rand_reset | 40.838m | 68.360ms | 3 | 200 | 1.50 |
| V3 | TOTAL | 3 | 200 | 1.50 | |||
| TOTAL | 601 | 920 | 65.33 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 16 | 13 | 10 | 62.50 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 89.03 | 95.76 | 93.95 | 100.00 | 71.05 | 91.67 | 99.49 | 71.33 |
UVM_ERROR (cip_base_vseq.sv:829) [hmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 115 failures:
1.hmac_stress_all_with_rand_reset.49900581802110946822640604800616319883933465484710006438716112931886924991793
Line 833, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 104812261 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 104812261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.hmac_stress_all_with_rand_reset.46870213512167905245165431578974025862633804257935770901337062633233952288879
Line 88543, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 27000851626 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 27000851626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 113 more failures.
UVM_FATAL (hmac_smoke_vseq.sv:139) [hmac_error_vseq] wait timeout occurred! has 44 failures:
2.hmac_error.29241524799177745981328349202488769138815131978361504529138727787080964659855
Line 5157, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_error/latest/run.log
UVM_FATAL @ 17882504170 ps: (hmac_smoke_vseq.sv:139) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] wait timeout occurred!
UVM_INFO @ 17882504170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.hmac_error.42164467409817471986223453055996353317645687458723383871930445241694733081003
Line 6905, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/3.hmac_error/latest/run.log
UVM_FATAL @ 10497749927 ps: (hmac_smoke_vseq.sv:139) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] wait timeout occurred!
UVM_INFO @ 10497749927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 27 more failures.
13.hmac_stress_all.115473155931935874073470376456253721399913530763815195803014194516807836053169
Line 31731, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/13.hmac_stress_all/latest/run.log
UVM_FATAL @ 30752786664 ps: (hmac_smoke_vseq.sv:139) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] wait timeout occurred!
UVM_INFO @ 30752786664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
16.hmac_stress_all.62001802435773901409926388891296084413171648307141189947857242660885752894425
Line 8707, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/16.hmac_stress_all/latest/run.log
UVM_FATAL @ 13177353837 ps: (hmac_smoke_vseq.sv:139) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] wait timeout occurred!
UVM_INFO @ 13177353837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
40.hmac_stress_all_with_rand_reset.101940748668374262429037495837135070848791657799818444161875375381049690923546
Line 25361, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/40.hmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 47415334589 ps: (hmac_smoke_vseq.sv:139) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] wait timeout occurred!
UVM_INFO @ 47415334589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
47.hmac_stress_all_with_rand_reset.94106292392933796438206924417770615274933002500899219846905894185417976970066
Line 2540, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/47.hmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 13140112386 ps: (hmac_smoke_vseq.sv:139) [uvm_test_top.env.virtual_sequencer.hmac_error_vseq] wait timeout occurred!
UVM_INFO @ 13140112386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.
UVM_ERROR (hmac_scoreboard.sv:346) [scoreboard] Check failed real_digest_val == exp_digest[digest_idx+*] (* [*] vs * [*]) has 39 failures:
2.hmac_wipe_secret.54248253165370120672745917504831843711660919265581552760183996627990757189816
Line 2067, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_wipe_secret/latest/run.log
UVM_ERROR @ 191846078 ps: (hmac_scoreboard.sv:346) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (1673012008 [0x63b82328] vs 1888546141 [0x7090ed5d])
UVM_INFO @ 191846078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.hmac_wipe_secret.29535773885353269849403321247238974221804729148111679752053410888985272829019
Line 832, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/4.hmac_wipe_secret/latest/run.log
UVM_ERROR @ 490597465 ps: (hmac_scoreboard.sv:346) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (2789966355 [0xa64b8213] vs 2978336006 [0xb185cd06])
UVM_INFO @ 490597465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
2.hmac_stress_all.27503288104574543822833804780456964844224935465883537370465830496982259044040
Line 142604, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/2.hmac_stress_all/latest/run.log
UVM_ERROR @ 102230020343 ps: (hmac_scoreboard.sv:346) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (2125898731 [0x7eb6a3eb] vs 949398609 [0x3896ac51])
UVM_INFO @ 102230020343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.hmac_stress_all.114816345967070898629168975201835510740439642370415810047938497509257783441280
Line 87013, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/5.hmac_stress_all/latest/run.log
UVM_ERROR @ 27536924350 ps: (hmac_scoreboard.sv:346) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (1879825250 [0x700bdb62] vs 571030829 [0x22093d2d])
UVM_INFO @ 27536924350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
7.hmac_stress_all_with_rand_reset.38576007938251106633036058092076124677046442300575254491595645887102784217829
Line 6082, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/7.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 15793705338 ps: (hmac_scoreboard.sv:346) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (3690440513 [0xdbf7a741] vs 1867900487 [0x6f55e647])
UVM_INFO @ 15793705338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
16.hmac_stress_all_with_rand_reset.58803332537775433032728314623840257564426156007027799184601459249151498935550
Line 2906, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/16.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 951831755 ps: (hmac_scoreboard.sv:346) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (3734690970 [0xde9adc9a] vs 3928421409 [0xea26f421])
UVM_INFO @ 951831755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 17 more failures.
UVM_ERROR (hmac_scoreboard.sv:336) [scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (* [*] vs * [*]) has 33 failures:
0.hmac_wipe_secret.27902330552409887754700095016272162516656938164011079585153382950703926217066
Line 834, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_wipe_secret/latest/run.log
UVM_ERROR @ 484037223 ps: (hmac_scoreboard.sv:336) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (2672949656 [0x9f51f998] vs 721402667 [0x2affbb2b])
UVM_INFO @ 484037223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.hmac_wipe_secret.96458601073713516122108526778285406142917704693418121601218995537246474844070
Line 2596, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/5.hmac_wipe_secret/latest/run.log
UVM_ERROR @ 4072838891 ps: (hmac_scoreboard.sv:336) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (2201960540 [0x833f405c] vs 1405217522 [0x53c1eaf2])
UVM_INFO @ 4072838891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
6.hmac_stress_all_with_rand_reset.4585109256045770927668246758417480015902833701481901777758398956319785441876
Line 19800, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/6.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4385827653 ps: (hmac_scoreboard.sv:336) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (1291520604 [0x4cfb0a5c] vs 903971791 [0x35e183cf])
UVM_INFO @ 4385827653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.hmac_stress_all_with_rand_reset.50300687427610444652229499977263444080335076181060105663670911592205448471681
Line 2612, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/11.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2181719407 ps: (hmac_scoreboard.sv:336) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (1961334596 [0x74e79744] vs 982119330 [0x3a89f3a2])
UVM_INFO @ 2181719407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 13 more failures.
9.hmac_stress_all.104519453910683728944318237800072298091157282469006785239622055653549313213763
Line 206028, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/9.hmac_stress_all/latest/run.log
UVM_ERROR @ 86494104051 ps: (hmac_scoreboard.sv:336) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (1432639 [0x15dc3f] vs 269885398 [0x10161fd6])
UVM_INFO @ 86494104051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.hmac_stress_all.9917358949548600792149063877024142676409710754982312728986244973415946070086
Line 3140, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/11.hmac_stress_all/latest/run.log
UVM_ERROR @ 308861137 ps: (hmac_scoreboard.sv:336) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (2970308163 [0xb10b4e43] vs 3477851810 [0xcf4bcea2])
UVM_INFO @ 308861137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (hmac_scoreboard.sv:333) [scoreboard] Check failed real_digest_val == exp_digest[digest_idx+*] (* [*] vs * [*]) has 32 failures:
0.hmac_stress_all.81587466482157699239461673913377168988974575621312150952115889325181428501408
Line 21480, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all/latest/run.log
UVM_ERROR @ 769838915 ps: (hmac_scoreboard.sv:333) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (3140436048 [0xbb2f4050] vs 684850274 [0x28d1fc62])
UVM_INFO @ 769838915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.hmac_stress_all.59168804743643193509738885633581279341807489860156141972686364941883256589472
Line 4608, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/4.hmac_stress_all/latest/run.log
UVM_ERROR @ 13620558961 ps: (hmac_scoreboard.sv:333) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (0 [0x0] vs 486091197 [0x1cf929bd])
UVM_INFO @ 13620558961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
0.hmac_stress_all_with_rand_reset.53912075226262312792716570946317973600744326038306568389804177611964116048459
Line 42459, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2803723594 ps: (hmac_scoreboard.sv:333) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (2245335379 [0x85d51953] vs 1491723204 [0x58e9e3c4])
UVM_INFO @ 2803723594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
21.hmac_stress_all_with_rand_reset.38099264377444383031554157879852259228732136089139602331602143714568011777899
Line 5691, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/21.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4936862590 ps: (hmac_scoreboard.sv:333) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (2749088702 [0xa3dbc3be] vs 15733006 [0xf0110e])
UVM_INFO @ 4936862590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 13 more failures.
1.hmac_wipe_secret.80354426445814237054118215629173996127542509842397497285059882200298510531474
Line 3031, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_wipe_secret/latest/run.log
UVM_ERROR @ 2980416821 ps: (hmac_scoreboard.sv:333) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (1401189084 [0x538472dc] vs 800275285 [0x2fb33b55])
UVM_INFO @ 2980416821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.hmac_wipe_secret.95071062839528876593525821805917505751967917413089633712859216714043405526270
Line 1525, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/6.hmac_wipe_secret/latest/run.log
UVM_ERROR @ 69230720 ps: (hmac_scoreboard.sv:333) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx+1] (767889772 [0x2dc5116c] vs 3472443345 [0xcef947d1])
UVM_INFO @ 69230720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
UVM_ERROR (hmac_scoreboard.sv:349) [scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (* [*] vs * [*]) has 25 failures:
3.hmac_wipe_secret.80344821416009808159936227129430839176865429475843751103069673568452576195156
Line 3918, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/3.hmac_wipe_secret/latest/run.log
UVM_ERROR @ 1171322094 ps: (hmac_scoreboard.sv:349) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (2491850588 [0x94869f5c] vs 1568576302 [0x5d7e932e])
UVM_INFO @ 1171322094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.hmac_wipe_secret.43889110016099657672637978278536599725712337814461697192827122831482255495046
Line 825, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/9.hmac_wipe_secret/latest/run.log
UVM_ERROR @ 645616448 ps: (hmac_scoreboard.sv:349) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (1935325970 [0x735abb12] vs 19476355 [0x1292f83])
UVM_INFO @ 645616448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
10.hmac_stress_all_with_rand_reset.29068764412540469067318550738429196670338289224418280169872448518069398386092
Line 497, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/10.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 252776352 ps: (hmac_scoreboard.sv:349) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (1400987760 [0x53816070] vs 1364901260 [0x515abd8c])
UVM_INFO @ 252776352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.hmac_stress_all_with_rand_reset.103529439674702324239162124469753404440952070352057283989798492127755841577370
Line 34172, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/14.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 76655531033 ps: (hmac_scoreboard.sv:349) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (3096870110 [0xb8967cde] vs 4246065106 [0xfd15cfd2])
UVM_INFO @ 76655531033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
14.hmac_stress_all.78499782689406927480521094382871011377471713678925848017098333291224617701238
Line 222243, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/14.hmac_stress_all/latest/run.log
UVM_ERROR @ 78172836475 ps: (hmac_scoreboard.sv:349) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (0 [0x0] vs 4069027524 [0xf2886ec4])
UVM_INFO @ 78172836475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
26.hmac_stress_all.15651350260394811142452384423636199520418104299062501483237702308992275185281
Line 32288, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/26.hmac_stress_all/latest/run.log
UVM_ERROR @ 10119511173 ps: (hmac_scoreboard.sv:349) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (1084805030 [0x40a8cfa6] vs 1497955723 [0x5948fd8b])
UVM_INFO @ 10119511173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_FATAL (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=*) == * has 15 failures:
0.hmac_error.71653508536971606520165702092528864242390761336881599554652217326948336558268
Line 2727, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/0.hmac_error/latest/run.log
UVM_FATAL @ 10299098078 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=0xd13ca000) == 0x1
UVM_INFO @ 10299098078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.hmac_error.64742657918708967027512793351601009740985787870576476807917264768210996403158
Line 1218, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/1.hmac_error/latest/run.log
UVM_FATAL @ 10100681292 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=0x8a91e000) == 0x1
UVM_INFO @ 10100681292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
10.hmac_stress_all.17973674091792332785594964472839940544994596499522831328742257365617300970025
Line 263, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/10.hmac_stress_all/latest/run.log
UVM_FATAL @ 10012321018 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=0xc0a56000) == 0x1
UVM_INFO @ 10012321018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.hmac_stress_all.93223346999846053814487079151934657504246112242474927213537922590331189402505
Line 16472, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/15.hmac_stress_all/latest/run.log
UVM_FATAL @ 11144997505 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=0x9fbb2000) == 0x1
UVM_INFO @ 11144997505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
142.hmac_stress_all_with_rand_reset.33755327130002696940003579966578508540234233264134807054898842679174638311162
Line 56415, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/142.hmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 23323351910 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=0x9994c000) == 0x1
UVM_INFO @ 23323351910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
153.hmac_stress_all_with_rand_reset.31674333019915238242290093968029094819145985169576651326601667649226455702076
Line 143698, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/153.hmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 34660986137 ps: (csr_utils_pkg.sv:576) [csr_utils::csr_spinwait] timeout hmac_reg_block.intr_state.hmac_err (addr=0xf347c000) == 0x1
UVM_INFO @ 34660986137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (hmac_scoreboard.sv:312) [scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (* [*] vs * [*]) has 10 failures:
6.hmac_stress_all.699244417303759529692826450841436245837391508543832878436451270937062354215
Line 17343, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/6.hmac_stress_all/latest/run.log
UVM_ERROR @ 3857847161 ps: (hmac_scoreboard.sv:312) [uvm_test_top.env.scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (0 [0x0] vs 0 [0x0])
UVM_INFO @ 3857847161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
18.hmac_stress_all.53272697711331657183290076039872922929988850735911135942789725583268917616512
Line 96235, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/18.hmac_stress_all/latest/run.log
UVM_ERROR @ 5064902728 ps: (hmac_scoreboard.sv:312) [uvm_test_top.env.scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (0 [0x0] vs 0 [0x0])
UVM_INFO @ 5064902728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
28.hmac_stress_all_with_rand_reset.60297088714211599746053458245220439326327639100653341662497484467406623112482
Line 189085, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/28.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 67530975312 ps: (hmac_scoreboard.sv:312) [uvm_test_top.env.scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (0 [0x0] vs 0 [0x0])
UVM_INFO @ 67530975312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
73.hmac_stress_all_with_rand_reset.73159137290847934466128838961859986986837775403823869845962411655567639237286
Line 23415, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/73.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4513683729 ps: (hmac_scoreboard.sv:312) [uvm_test_top.env.scoreboard] Check failed real_digest_val != exp_digest[digest_idx] (0 [0x0] vs 0 [0x0])
UVM_INFO @ 4513683729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (hmac_scoreboard.sv:635) [scoreboard] Check failed cfg.hmac_vif.is_idle() == val (* [*] vs * [*]) has 3 failures:
Test hmac_stress_all has 2 failures.
3.hmac_stress_all.6820347999183683806920463431109663223105571940967219269995529311664547365731
Line 2834, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/3.hmac_stress_all/latest/run.log
UVM_ERROR @ 857194719 ps: (hmac_scoreboard.sv:635) [uvm_test_top.env.scoreboard] Check failed cfg.hmac_vif.is_idle() == val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 857194719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
43.hmac_stress_all.45676720169423489057793568952952285913734323128251022853807929751990549214873
Line 45559, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/43.hmac_stress_all/latest/run.log
UVM_ERROR @ 30699676690 ps: (hmac_scoreboard.sv:635) [uvm_test_top.env.scoreboard] Check failed cfg.hmac_vif.is_idle() == val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 30699676690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test hmac_stress_all_with_rand_reset has 1 failures.
103.hmac_stress_all_with_rand_reset.98685037084702954995862936002256682916348612162817971422474405562008704068797
Line 235854, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/103.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 25272060262 ps: (hmac_scoreboard.sv:635) [uvm_test_top.env.scoreboard] Check failed cfg.hmac_vif.is_idle() == val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 25272060262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (hmac_scoreboard.sv:324) [scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (* [*] vs * [*]) has 2 failures:
6.hmac_error.87331284575058553222633666373437449281615115854438138944502294284936359328516
Line 6518, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/6.hmac_error/latest/run.log
UVM_ERROR @ 506235189 ps: (hmac_scoreboard.sv:324) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (0 [0x0] vs 2714095028 [0xa1c5cdb4])
UVM_INFO @ 506235189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.hmac_error.57893796926199690019711979813625668419662564991944083149071678846203114502690
Line 20233, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/20.hmac_error/latest/run.log
UVM_ERROR @ 7037588970 ps: (hmac_scoreboard.sv:324) [uvm_test_top.env.scoreboard] Check failed real_digest_val == exp_digest[digest_idx] (0 [0x0] vs 45600311 [0x2b7ce37])
UVM_INFO @ 7037588970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:753) [hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
93.hmac_stress_all_with_rand_reset.25361920973665036637439130385220616108688833908068840748949875871231171567799
Line 3347, in log /container/opentitan-public/scratch/os_regression/hmac-sim-vcs/93.hmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 8203518983 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.hmac_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 8203518983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---